PM0223 datasheet(40/110 Pages) STMICROELECTRONICS

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The STM32L0 Cortex-M0+ Instruction Set

PM0223

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DocID025763 Rev 1

3.3

About the instruction descriptions

The following sections give more information about using the instructions:

•

Operands.

•

Restrictions when using PC or SP.

•

Shift Operations.

•

Address alignment.

•

PC-relative expressions.

•

Conditional execution.

3.3.1

Operands

An instruction operand can be an ARM register, a constant, or another instruction-specific

parameter. Instructions act on the operands and often store the result in a destination

the other operands.

3.3.2

Restrictions when using PC or SP

Many instructions are unable to use, or have restrictions on whether you can use, the

Program Counter (PC) or Stack Pointer (SP) for the operands or destination register. See

instruction descriptions for more information.

Note:

When you update the PC with a BX, BLX, or POP instruction, bit[0] of any address must be 1

for correct execution. This is because this bit indicates the destination instruction set, and

the STM32L0 Cortex-M0+ processor only supports Thumb instructions. When a BL or BLX

instruction writes the value of bit[0] into the LR it is automatically assigned the value 1.

3.3.3

Shift Operations

the shift length. Register shift can be performed directly by the instructions ASR, LSR, LSL,

and ROR and the result is written to a destination register.

The permitted shift lengths depend on the shift type and the instruction, see the individual

instruction description. If the shift length is 0, no shift occurs. Register shift operations

update the carry flag except when the specified shift length is 0. The following sub-sections

describe the various shift operations and how they affect the carry flag. In these

descriptions, Rm is the register containing the value to be shifted, and n is the shift length.

ASR

Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by

places, into the right-hand 32-n bits of the result, and it copies the original bit[31] of the

You can use the ASR operation to divide the signed value in the register Rm by 2n, with the

result being rounded towards negative-infinity.

When the instruction is ASRS the carry flag is updated to the last bit shifted out, bit[n-1], of

the register Rm

Note:

If n is 32 or more, then all the bits in the result are cleared to 0.

If n is 33 or more and the carry flag is updated, it is updated to 0.

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