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数据搜索系统，热门电子元器件搜索 |
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PC87366 数据表(PDF) 24 Page - National Semiconductor (TI) |
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PC87366 数据表(HTML) 24 Page - National Semiconductor (TI) |
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24 / 240 page  1.0 Signal/Pin Connection and Description (Continued) 24 www.national.com 1.4 DETAILED SIGNAL/PIN DESCRIPTIONS This section describes all signals, organized in functional groups. 1.4.1 ACCESS.bus Interface (ACB) 1.4.2 Bus Interface 1.4.3 Clock 1.4.4 Fan Speed Control and Monitor (FSCM) Signal Pin(s) I/O Buffer Type Power Well Description SCL 54 I/O INSM/OD6 VDD ACCESS.bus Clock Signal. An internal pull-up is optional, depending upon the ACCESS.bus configuration register. SDA 55 I/O INSM/OD6 VDD ACCESS.bus Data Signal. An internal pull-up is optional, depending upon the ACCESS.bus configuration register. Signal Pin(s) I/O Buffer Type Power Well Description LAD0-3 15-18 I/O INPCI/OPCI VDD LPC Address-Data. Multiplexed command, address bi- directional data and cycle status. LCLK 11 I INPCI VDD LPC Clock. Practically the PCI clock (up to 33 MHz) LDRQ 13 O OPCI VDD LPC DMA Request. Encoded DMA request for LPC I/F. LFRAME 14 I INPCI VDD LPC Frame. Low pulse indicates the beginning of new LPC cycle or termination of a broken cycle. LRESET 10 I INPCI VDD LPC Reset. Practically the PCI system reset. SERIRQ 12 I/O INPCI/OPCI VDD Serial IRQ. The interrupt requests are serialized over a single pin, where each internal IRQ signal is delivered during a designated time slot. SMI 21 OD OD12 VDD System Management Interrupt Signal Pin(s) I/O Buffer Type Power Well Description CLKIN 22 I INT VDD Clock In. 48 MHz clock input. Signal Pin(s) I/O Buffer Type Power Well Description FANIN0 FANIN1 FANIN2 4 2 128 I INTS VDD Fan Inputs. Used to feed the fan’s tachometer pulse to the Fan Speed Monitor. The rising edge indicates the completion of a half (or full) revolution of the fan. FANOUT0 FANOUT1 FANOUT2 5 3 1 O O2/14 VDD Fan Outputs. Pulse Width Modulation (PWM) signals, used to control the speed of cooling fans by controlling the voltage supplied to the fan’s motor. |
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