PC87366 datasheet(40/240 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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Control

The only implemented control register for each logical device is the Activate register at index 30h. Bit 0 of the Activate reg-

ister controls the activation of the associated function block. Activation of the block enables access to the block’s registers,

and attaches its system resources, which are unused as long as the block is not activated. Other effects may apply, on a

function-specific basis (such as clock enable and active pinout signaling).

Standard Conﬁguration

The standard configuration registers are used to manage the PnP resource allocation to the functional blocks. The I/O port

base address descriptor 0 is a pair of registers at Index 60-61h, holding the (first or only) 16-bit base address for the register

set of the functional block. An optional 16-bit second base-address (descriptor 1) at index 62-63h is used for logical devices

with more than one continuous register set. Interrupt Number and Wake-Up on IRQ Enable (index 70h) and IRQ Type Select

(index 71h) allocate an IRQ line to the block and control its type. DMA Channel Select 0 (index 74h) allocates a DMA channel

to the block, where applicable. DMA Channel Select 1 (index 75h) allocates a second DMA channel, where applicable.

Special Conﬁguration

The vendor-defined registers, starting at index F0h, are used to control function-specific parameters such as operation

modes, power saving modes, pin TRI-STATE, clock rate selection, and non-standard extensions to generic functions.

2.2.5

Default Configuration Setup

The default configuration setup of the PC87366 can include four reset types, described below. See specific register descrip-

tions for the bits affected by each reset type.

• Software Reset

This reset is enabled by bit 1 of the SIOCF1 register, which resets all logical devices. A software reset also resets most

bits in the SuperI/O control and configuration registers (see Section 2.8 for the bits not affected). This reset does not

affect register bits that are locked for write access.

• Hardware Reset

This reset is activated by the assertion of the LRESET input. It resets all logical devices, with the exception of the System

Wake-Up Control (SWC). It also resets all SuperI/O control and configuration registers, except for those that are battery-

backed.

• V

PP Power-Up Reset

This reset is activated when either VSB or VBAT is powered up after both have been off. VPP is an internal voltage which

is a combination of VSB and VBAT.VPP is taken from VSB if VSB is greater than the minimum (Min) value defined in the

Device Characteristics chapter; otherwise, VBAT is used as the VPP source. This reset resets all registers whose values

are retained by VPP.

• V

SB Power-Up Reset

This is an internally generated reset that resets the SWC, excluding those SWC registers whose values are retained by

VPP. This reset is activated after VSB is powered up.

In event of a hardware reset, the PC87366 wakes up with the following default configuration setup:

— The conﬁguration base address is 2Eh or 4Eh, according to the BADDR strap pin value, as shown in Table 5.

— The Keyboard Controller (KBC) is active and all other logical devices are disabled, with the exception of the SWC

which remains functional but whose registers cannot be accessed.

— All multiplexed GPIO pins, except for pins whose function is controlled by battery-backed registers and pins 8 and 9

(which are controlled by bits 1 and 0 of the SIOCF3 register) are conﬁgured as GPIO pins, with an internal static pull-

up (default direction is input).

In event of either a hardware or a software reset, the PC87366 wakes up with the following default configuration setup:

— The legacy devices are assigned with their legacy system resource allocation.

— The National proprietary functions are not assigned with any default resources and the default values of their base

addresses are all 00h.

2.2.6

Power States

The following terminology is used in this document to describe the various possible power states:

• Power On

Both VSB and VDD are active.

• Power Off

VSB is active and VDD is inactive.

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