PC87366 datasheet(53/240 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.8.10

SuperI/O Configuration B Register (SIOCFB)

This is a battery-backed register.

Location:

Index 2Bh

Type:

Varies per bit

Bit

Name

Reserved

Pins 47-49

Function

Select

Intrusion

Level

Intrusion

Status

LED Mode Control

Pin 59

Function

Select

Pin 58

Function

Select

Reset

Bit

Description

Reserved

Pins 47-49 Function Select

0: Pins 47-49 enabled as D1N, D1P and D2N by the TMS (default)

1 Pins 47-49 enabled as TS1, TS2 and TS3 by the VLM. For further details, see the TMS COnﬁguration

regster setting.

Intrusion Level. This is a RO bit, which reﬂects the value of pin 29 (CHASI), either 0 or 1.

Intrusion Status. Write 0 to this bit to clear it.

0: No intrusion

1: Intrusion detected (default at VPP power-up reset)

3-2

LED Mode Control. This is a R/W bit.

Bits

3 2

Function

0 0

Software mode (default at VPP power-up reset)

0 1

Hardware mode 1 (default when power supply control is disabled by PSLDC0,1 straps)

1 0

Hardware mode 2

1 1

Reserved

Pin 59 Function Select. This is a R/W bit.

0: GPIE7 (default at VPP power-up reset)

1: IRRX1

Pin 58 Function Select. This is a R/W bit.

0: GPIE6 (default at VPP power-up reset)

1: IRRX2_IRSL0

PC87366 数据表(PDF) 53 Page - National Semiconductor (TI)

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PC87366 数据表(PDF) 53 Page - National Semiconductor (TI)

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