PC87366 datasheet(50/240 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.8.6

SuperI/O Conﬁguration 5 Register (SIOCF5)

Location:

Index 25h

Type:

Varies per bit

2.8.7

SuperI/O Revision ID Register (SRID)

This register contains the identity number of the chip revision. SRID is incremented on each revision.

Location:

Index 27h

Type:

Bit

76543210

Name

VID0 and VID1

Route

Select

SMI to IRQ2

Enable

Reserved

Pin 128

Function

Select

Reset

00000000

Bit

Description

7-5

VID0 and VID1 Route Select. Deﬁnes the routing of GPIO inputs to the VLM VID register. This is a R/W

bit.

Bits

7 6 5

Route Select

0 0 0

VID0 and VID1 are not routed.

0 0 1

VID4-VID0 are routed from GPIO11-13, GPIO16, GPIO17. Only CPU0 is supported.

0 1 0

VID4-VID0 are routed from GPIO05, GPIO12-14, GPIO32 . Only CPU0 is supported.

0 1 1

When CPU0 is selected: VID4-VID0 are routed from GPIO20-24;

when CPU1 is selected: VID4-VID0 are routed from GPIO25-27, GPIO30, GPIO31

1 0 0

VID4-VID0 are routed from GPIO11-13, GPIO16, GPIO17; processor select control is routed to

GPIO14, which is configured as output.

Other

Reserved

SMI to IRQ2 Enable. This is a R/W bit.

0: Disabled (default)

1: Enabled

3-2

Reserved

1-0

Pin 128 Function Select. This is a R/W bit.

Bits

1 0

Function

0 0

GPIO33 (default)

0 1

FANIN2

1 x

Reserved

PC87366 数据表(PDF) 50 Page - National Semiconductor (TI)

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PC87366 数据表(PDF) 50 Page - National Semiconductor (TI)

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