PC87366 datasheet(9/240 Pages) NSC

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5.3.2

Fan Monitor Threshold Register (FMTHR) ................................................................ 128

5.3.3

Fan Monitor Speed Register (FMSPR) ...................................................................... 128

5.3.4

Fan Monitor Control and Status Register (FMCSR) .................................................. 128

5.4

FAN SPEED MONITOR BITMAP ............................................................................................ 129

6.0

General-Purpose Input/Output (GPIO) Port

6.1

OVERVIEW ............................................................................................................................. 130

6.2

BASIC FUNCTIONALITY ........................................................................................................ 131

6.2.1

Configuration Options ................................................................................................ 131

6.2.2

Operation ................................................................................................................... 131

6.3

EVENT HANDLING AND SYSTEM NOTIFICATION .............................................................. 132

6.3.1

Event Configuration ................................................................................................... 132

6.3.2

System Notification .................................................................................................... 132

6.4

GPIO PORT REGISTERS ....................................................................................................... 133

6.4.1

GPIO Pin Configuration (GPCFG) Register .............................................................. 134

6.4.2

GPIO Pin Event Routing (GPEVR) Register ............................................................. 135

6.4.3

GPIO Port Runtime Register Map ............................................................................. 135

6.4.4

GPIO Data Out Register (GPDO) .............................................................................. 136

6.4.5

GPIO Data In Register (GPDI) .................................................................................. 136

6.4.6

GPIO Event Enable Register (GPEVEN) .................................................................. 137

6.4.7

GPIO Event Status Register (GPEVST) .................................................................... 137

7.0

WATCHDOG Timer (WDT)

7.1

OVERVIEW ............................................................................................................................. 138

7.2

FUNCTIONAL DESCRIPTION ................................................................................................ 138

7.3

WATCHDOG TIMER REGISTERS ......................................................................................... 139

7.3.1

WATCHDOG Timer Register Map ............................................................................. 139

7.3.2

WATCHDOG Timeout Register (WDTO) .................................................................. 139

7.3.3

WATCHDOG Mask Register (WDMSK) .................................................................... 140

7.3.4

WATCHDOG Status Register (WDST) ...................................................................... 141

7.4

WATCHDOG TIMER REGISTER BITMAP ............................................................................. 141

8.0

ACCESS.bus Interface (ACB)

8.1

OVERVIEW ............................................................................................................................. 142

8.2

FUNCTIONAL DESCRIPTION ................................................................................................ 142

8.2.1

Data Transactions ..................................................................................................... 142

8.2.2

Start and Stop Conditions .......................................................................................... 142

8.2.3

Acknowledge (ACK) Cycle ........................................................................................ 143

8.2.4

Acknowledge after Every Byte Rule .......................................................................... 144

8.2.5

Addressing Transfer Formats .................................................................................... 144

8.2.6

Arbitration on the Bus ................................................................................................ 144

8.2.7

Master Mode .............................................................................................................. 145

8.2.8

Slave Mode ................................................................................................................ 147

8.2.9

Configuration ............................................................................................................. 147

PC87366 数据表(PDF) 9 Page - National Semiconductor (TI)

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