 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
PC87366 数据表(PDF) 27 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
PC87366 数据表(HTML) 27 Page - National Semiconductor (TI) |
|
|
27 / 240 page  1.0 Signal/Pin Connection and Description (Continued) 27 www.national.com 1.4.9 Keyboard and Mouse Controller (KBC) 1.4.10 Musical Instrument Digital Interface (MIDI) Port Signal Pin/s I/O Buffer Type Power Well Description GA20 9 I/O INT/OD2 VDD Gate A20. KBC gate A20 (P21) output. KBCLK 111 I/O INTS/OD14 VDD,VSB Keyboard Clock. Transfers the keyboard clock between the SuperI/O chip and the external keyboard using the PS/2 protocol. This pin is driven by the internal, inverted KBC P26 signal, and is connected internally to the T0 signal of the KBC. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage. KBDAT 112 I/O INTS/OD14 VDD,VSB Keyboard Data. Transfers the keyboard data between the SuperI/O chip and the external keyboard using the PS/2 protocol. This pin is driven by the internal, inverted KBC P27 signal, and is connected internally to KBC P10. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage. KBRST 8 I/O INT/OD2 VDD KBD Reset. Keyboard Reset (P20) output. MCLK 113 I/O INTS/OD14 VDD,VSB Mouse Clock. Transfers the mouse clock between the SuperI/O chip and the external keyboard using the PS/2 protocol. This pin is driven by the internal, inverted KBC P23 signal, and is connected internally to KBC T1. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage. MDAT 114 I/O INTS/OD14 VDD,VSB Mouse Data. Transfers the mouse data between the SuperI/O chip and the external keyboard using the PS/2 protocol. This pin is driven by the internal, inverted KBC P22 signal, and is connected internally to KBC P11. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage. P12, P16, P17 6,127, 7 I/O INT/OD2 VDD I/O Port. KBC open-drain signal for general-purpose input and output, controlled by KBC firmware. Signal Pin(s) I/O Buffer Type Power Well Description MDTX 125 O O3/6 VDD MIDI Transmit. MIDI serial data output. MDRX 126 I INTS VDD MIDI Receive. MIDI serial data input. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
