PC87366 datasheet(42/240 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.3.3

GPIO Pin Function Lock

The PC87366 is capable of locking the attributes of each GPIO or Standby GPIO pin. The following attributes can be locked:

Output enable

Output type

Static pull-up

Driven data.

GPIO pins are locked per pin by setting the Lock bit in the appropriate GPIO Pin Configuration register. When the Lock bit

is set, the configuration of the associated GPIO pin can only be released by a hardware reset.

Standby GPIO pins are locked in the same manner by setting the Lock bit in the appropriate Standby GPIO Pin Configuration

registers. However, once a Standby GPIO pin is locked, its locked attributes can only be released with a VSB power-up reset.

2.4

POWER SUPPLY CONTROL (PSC)

The PC87366 includes hardware that can be used to ease the system’s control over the computer’s power supply. This hard-

ware is implemented as a state machine that determines the required state of the power supply based on several input sig-

nals, and also connects to the system’s ACPI controller to share information about the system’s power state via specific

interface signals.

The PSC uses the pin functions SLPS3, SLPS5, PWBTIN, PWBTOUT and PSON. These functions are optional on their

respective pins and must be selected to enable the PSC by setting the values of the PSLDC0,1 strap pins (see Table 14).

Once enabled, the PSC can be operated in one of two modes, according to the value of bit 0 (Power Button Mode) of the

SIOCFD register:

ACPI mode

Legacy mode

ACPI Mode

When the PSC is operated in ACPI mode (bit 0 of the SIOCFD register is set to 1), the ACPI controller of the system controls

the system’s power supply by means of the SLPS3 state. When SLPS3 is set to 0, the power supply turns off; when it is set

to 1, the power supply turns on. The state of the PSON output signal (either ON or OFF) is identical to the state of the SLPS3

input signal. The polarity of PSON is set by the PSONPOL strap.

The only case in which the PSC affects the value of the PSON output is when a Crowbar condition occurs. A Crowbar con-

dition is defined as the state in which PSON has been active for a certain period of time, but the system’s power supply

remains inactive. In this case, PSON is forced inactive, and the PWBTOUT output is pulsed to indicate to the ACPI controller

that SLPS3 must be driven low, thus indirectly inactivating PSON and preventing a deadlock. For a detailed description of

the Crowbar mechanism, see “Crowbar Condition” below.

In ACPI mode, during regular operation, the PWBTOUT output is pulsed when either of the following events occurs:

PWBTIN is pulsed.

A wake-up event, that is routed to PWBTOUT.

A wake-up event that is routed to the power button output can cause PWBTOUT to be pulsed in ACPI mode if one of the

following conditions is met:

SLPS5 is active.

Enable Power Button Pulse on S3 (bit 3) of the SWC WK_CFG register is set to 1.

However, when in ACPI mode, PWBTIN and PWBTOUT activity has no effect on the PSON output. The power button mech-

anism can have an indirect effect on PSON only if PWBTOUT is connected to the power button input of the ACPI controller,

thus affecting the SLPS3 signal.

Legacy Mode

When the PSC is operated in Legacy mode (bit 0 of the SIOCFD register is set to 0), the PC87366 controls the system’s

power supply. In this mode, the PSON output signal is set by the PC87366 according to the following factors: the state of

input signals, the state of the power supply lines, power button activity and certain configuration bits. Although the ACPI con-

troller does not control the system’s power supply, it tracks the system’s power state. For this purpose, the PC87366 ma-

PC87366 数据表(PDF) 42 Page - National Semiconductor (TI)

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