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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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PC87366 数据表(PDF) 76 Page - National Semiconductor (TI) |
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PC87366 数据表(HTML) 76 Page - National Semiconductor (TI) |
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76 / 240 page  2.0 Device Architecture and Configuration (Continued) 76 www.national.com 2.17.4 Fan Speed Control and Monitor Configuration 2 Register This register is reset by hardware to 00h. Location: Index F1h Type: R/W 2.17.5 Fan Speed Control OTS Configuration Register Location: Index F2h Type: R/W Bit 76543210 Name Reserved Fan Speed Invert 2 Enable Fan Speed Control 2 Enable Fan Speed Monitor 2 Enablel Reset 00000000 Bit Description 7-3 Reserved 2 Fan Speed Invert 2 Enable 0: Disabled (default) 1: Enabled 1 Fan Speed Control 2 Enable 0: Disabled (default) 1: Enabled 0 Fan Speed Monitor 2 Enable 0: Disabled (default) 1: Enabled Bit 76543210 Name Reserved Fan 2 Enable on OTS Fan 1 Enable on OTS Fan 0 Enable on OTS Reset 00000000 Bit Description 7-3 Reserved 2 Fan 2 Enable on OTS. Enables fan 2 at 100% duty cycle when an OTS event becomes active. 0: Fan 2 operates as defined by the PWM mechanism 1: Fan 2 is forced to 100% duty cycle when the OTS output form any of the temperature mesurement channels (TMS or VLM) becomes active. 1 Fan 1 Enable on OTS. Enables fan 1 at 100% duty cycle when an OTS event becomes active. 0: Fan 1 operates as defined by the PWM mechanism 1: Fan 1 is forced to 100% duty cycle when the OTS output form any of the temperature mesurement channels (TMS or VLM) becomes active. 0 Fan 0 Enable on OTS. Enables fan 0 at 100% duty cycle when an OTS event becomes active. 0: Fan 0 operates as defined by the PWM mechanism 1: Fan 0 is forced to 100% duty cycle when the OTS output form any of the temperature mesurement channels (TMS or VLM) becomes active. |
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