PC87366 datasheet(41/240 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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• Power Fail

Both VSB and VDD are inactive.

Note:

The following state is illegal: VDD active and VSB inactive.

2.2.7

Address Decoding

A full 16-bit address decoding is applied when accessing the configuration I/O space as well as the registers of the functional

blocks. However, the number of configurable bits in the base address registers varies for each logical device.

The lower 1, 2, 3, 4 or 5 address bits are decoded within the functional block to determine the offset of the accessed register,

within the logical device’s I/O range of 2, 4, 8, 16 or 32 bytes, respectively. The rest of the bits are matched with the base

address register to decode the entire I/O range allocated to the logical device. Therefore the lower bits of the base address

register are forced to 0 (read only), and the base address is forced to be 2, 4, 8, 16 or 32 byte-aligned, according to the size

of the I/O range.

The base address of the FDC, Serial Port 1, Serial Port 2 with IR and KBC are limited to the I/O address range of 00h to

7FXh only (bits 11-15 are forced to 0). The Parallel Port base address is limited to the I/O address range of 00h to 3F8h.

The addresses of the non-legacy logical devices, including the GMP and the MIDI, are configurable within the full 16-bit ad-

dress range (up to FFFXh).

In some special cases, other address bits are used for internal decoding (such as bit 2 in the KBC and bit 10 in the Parallel

Port). The KBC has two I/O descriptors with some implied dependency between them. For more details, see the description

of the base address register for each logical device.

2.3

PROTECTION

The PC87366 provides features to protect the PC at mechanical and software levels.

At the mechanical level, the device can detect intrusion to the chassis of the PC.

At the software level, the device can be locked to protect configuration bits or alteration of the hardware configuration of the

device, as well as internal GPIO settings and several types of configuration settings.

All protection mechanisms can optionally be used.

2.3.1

Chassis Intrusion Detection

The Chassis Intrusion Detection mechanism is based on the state of pin 29, CHASI. This pin reflects the status of an external

switch that indicates the PC chassis state.

Bits 4,5 of the SIOCFB register monitor this pin, and provide two types of information. Bit 4 reports a previously detected

chassis intrusion, defined as any kind of transition on the CHASI pin. Bit 5 reflects the momentary value of the CHASI pin.

For further details on the SIOCFB register, see Section 2.8.10.

To prevent the CHASI pin from detecting a false chassis intrusion, it is implemented with an internal noise filter.

A chassis intrusion event can be reported to the host system by either software or hardware. When using software, the sys-

tem must read the SIOCFB register to check if an intrusion event has occurred. When using hardware, the device provides

the following means for indicating chassis intrusion:

Dedicated output (CHASO)

SMI assertion.

To use the CHASO function, it must first be selected by setting bit 6 of the SIOCFA register to 1. Thereafter, whenever a

chassis intrusion is detected, the CHASO pin reflects the value of bit 4 of the SIOCFB register. When bit 4 of this register is

set to 1, the CHASO pin is asserted (driven low). It is deasserted when this bit is cleared.

To use the SMI assertion, it must either be selected on its pin or routed to interrupt request channel 2. To select SMI on its

pin, set bit 2 of the SIOCF3 register to 1 (for further details, see Section 2.8.4). To route the SMI signal to interrupt request

channel 2, set bit 4 of the SIOCF5 register to 1 (for further details, see Section 2.8.6). In addition, the chassis intrusion event

must be routed to the SMI signal by setting bit 5 of the SIOCF8 register to 1 (for further details, see Section 2.8.8). Thereafter,

whenever a chassis intrusion is detected, the SMI signal reflects bit 4 of the SIOCFB register. When bit 4 of this register is

set to 1, the SMI signal and the selected target indication are asserted (driven low). The SMI signal is deasserted when this

bit 4 is cleared.

2.3.2

Pin Configuration Lock

To lock the pin configuration of the PC87366 in order to prevent unwanted changes to hardware configuration, set bit 7 of

the SIOCF1 register to 1. Setting this bit causes all function select configuration bits, including those that are battery backed,

to become read only bits. This bit can only be cleared by a hardware reset.

PC87366 数据表(PDF) 41 Page - National Semiconductor (TI)

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