PC87366 datasheet(60/240 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.10.2

Logical Device 1 (PP) Configuration

Table 21 lists the configuration registers which affect the Parallel Port. Only the last register (F0h) is described here. See

Sections 2.2.3 and 2.2.4 for descriptions of the others.

Table 21. Parallel Port Conﬁguration Registers

2.10.3

Parallel Port Configuration Register

This register is reset by hardware to F2h.

Location:

Index F0h

Type:

R/W

Index

Conﬁguration Register or Action

Type

Reset

30h Activate. See also bit 0 of the SIOCF1 register.

R/W

00h

60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. Bit 2 (for

A10) should be 0b.

R/W

02h

61h Base Address LSB register. Bits 1 and 0 (A1 and A0) are read only, 00b. For ECP

Mode 4 (EPP) or when using the Extended registers, bit 2 (A2) should also be 0b.

R/W

78h

70h Interrupt Number and Wake-Up on IRQ Enable register

R/W

07h

71h Interrupt Type

Bits 7-2 are read only.

Bit 1 is a read/write bit.

Bit 0 is read only. It reﬂects the interrupt type dictated by the Parallel Port operation

mode. This bit is set to 1 (level interrupt) in Extended Mode and cleared (edge

interrupt) in all other modes.

R/W

02h

74h DMA Channel Select

R/W

04h

75h Report no second DMA assignment

04h

F0h Parallel Port Conﬁguration register

R/W

F2h

Bit

76543210

Name

Reserved

Extended

Access

Reserved

Power

Mode

Control

TRI-STATE

Control

Reset

11110010

Required

Bit

Description

7-5

Reserved. Must be 11.

Extended Register Access

0: Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are ignored).

1: Registers at base (address) + 403h, base + 404h and base + 405h are accessible. This option supports run-

time conﬁguration within the Parallel Port address space.

3-2

Reserved

Power Mode Control. When the logical device is active:

0: Parallel port clock disabled. ECP modes and EPP time-out are not functional when the logical device is active.

Registers are maintained.

1: Parallel port clock enabled. All operation modes are functional when the logical device is active (default).

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

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PC87366 数据表(PDF) 60 Page - National Semiconductor (TI)

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