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PC87366 数据表(PDF) 82 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 PC87366
功能描述  128-Pin LPC SuperI/O with System Hardware Monitoring, MIDI and Game Ports
PDF  240 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

PC87366 数据表(HTML) 82 Page - National Semiconductor (TI)

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3.0 System Wake-Up Control (SWC) (Continued)
82
www.national.com
In addition to the event detection and system notification capabilities, the SWC operates several general-purpose I/O pins
powered by VSB. These pins can be used to perform various tasks while VSB is present and VDD is not.
3.2
FUNCTIONAL DESCRIPTION
The SWC monitors 16 system events or activities. Upon entering the SWC, the events pass through a filter (where applica-
ble) and polarity adjustment logic. After filtering and polarity adjustment, each event enters the Wake-Up Mode Control (Ex-
tension) Logic which determines its effect during the various system power states. The Wake-Up Mode Control (Extension)
Logic also controls the effect of each wake-up event on the power button output (PWBTOUT). See Figure 7 for an illustration
of this mechanism.
After the wake-up mode is determined for all events, each one of them is fed into a dedicated detector that determines when
this event is active, according to predetermined (either fixed or programmable) criteria. A set of dedicated registers is used
to determine the wake-up criteria, including the CEIR address and the keyboard sequence.
Two Wake-Up Events Status registers (WK_STSn) hold a Status bit for each of the 16 events.
Six Wake-Up Events Routing Control register s (WK_ENn WK_SMIENn and WK_IRQENn) hold three Routing Enable bits
for each of the 16 events, to allow selective routing of these events to PWUREQ, SMI and/or the assigned SWC interrupt
request (IRQ) channel.
Upon detection of any active event, the corresponding Status bit is set to 1, regardless of any Routing Enable bit. If both the
Status bit and a Routing Enable bit corresponding to a specific event are set to 1 (no matter in what order), the output pin
corresponding to that Routing Enable bit is asserted. The Status bit is deasserted by writing 1 to it. Writing 0 to a Routing
Enable bit of an event prevents it from issuing the corresponding system notification, but does not affect the Status bit. Figure
8 show the routing scheme of detected wake-up events to the various means of system notification.
Figure 8. Wake-Up Events Routing Scheme
To enable the assertion of SMI by detected wake-up events, it is necessary to either select the SMI function on a device pin
or route it to an interrupt request channel via the device’s configuration registers.
Event i
Detection
WK_SMIENn.i
WK_IRQENn.i
WK_ENn.i
Wake-Up Event i
From Wake-Up
PWUREQ
SMI
IRQ
Event
Routing
Logic
WK_STSn.i
Extesion Logic



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