PC87366 datasheet(44/240 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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Table 13. PSON VSB Power-Up Default State

Crowbar Condition

A Crowbar condition is a situation in which the signal that directly controls the system’s power supply is active for a certain

duration of time, without a power supply response. To prevent this deadlock and enable reactivation of the power supply, a

special crowbar mechanism is included in the PSC logic.

Once the PSON is activated, assuming the power supply is off, a timer in the PSC logic starts counting. If this timer reaches

its terminal count before the power supply becomes active, the PSC detects a Crowbar condition. In this case, PSON is

deactivated and the PSC makes sure that the ACPI state of the system is changed to OFF.

The time that causes a Crowbar condition is defined as the Crowbar Timeout. The Crowbar Timeout of the PSC can be pro-

grammed to values between 0.5-2.25 seconds. This Timeout value is set by writing the appropriate value to bit 4-3 of the

SIOCFD register. For further details, refer to the description of this register in Section 2.8.12.

2.5

LED OPERATION AND STATES

The device supports up to two LEDs, depending on Pin 25 and Pin 26 Function Select (bits 1-2 and bit 3) of the SIOCFA

, when in power-on state. The device also provides modes for hardware LED control. This enables the LEDs to support fea-

tures such as power and error indication.

The LEDs may be operated in software, hardware1 or hardware 2 modes. These modes are set by LED Mode Control (bits

2 and 3) of the SIOCFB register. Each LED can be set to On, Off or to blink at different rates by means of bits 0-2 (LED1)

and bits 3-5 (LED2) of the SIOCFC register. When in power-on state (both VDD and VSB exist), the LEDs are software-con-

trolled. When in power fail state (no VSB and no VDD) the LEDs are off. Table 14 shows the effect of hardware modes 1 and

2 on LED operation that override the above rules.

Table 14. Hardware Modes 1 and 2 Effect on LED Operation

2.6

POWER SUPPLY CONTROL AND LED CONFIGURATION

A combination of two strap pins (Power Supply and LED Configuration 0 and 1, PSLDC0,1, pins 99 and 107 respectively)

determines the configuration of the power supply control pins and LEDs. Both pins 99 and 107 have weak pull-downs, and

are sampled on VSB power-up reset. Table 15 describes how they affect the chip configuration.

Resume Last

PSON State

(SIOCFD, Bit 2)

Last PSON

State

PSON VSB Power-Up

Default

Same as SLPS3 state

Mode

System State

LED1

LED2

Hardware 1

(SIOCFB, bits 3-2=01)

VSB power-up reset

Off

1 Hz blink, 50% duty cycle

Power off (VSB,noVDD)

Software-controlled

1 Hz blink, 50% duty cycle

Hardware 2

(SIOCFB, bits 3-2=10)

ACPI mode and

Sleep State 3

Software-controlled

ACPI mode, Sleep State 5,

bit 6 = 1 in SIOCFC register

and Power Supply Control

enabled

Software-controlled

ACPI mode, any other

conﬁguration

Off

Legacy mode and power off

(no VDD)

Off

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