PC87366 datasheet(180/240 Pages) NSC

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11.0 Voltage Level Monitor (VLM) (Continued)

180

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ALERT Response Read Sequence

When the VLM activates its ALERT output, the host should respond by reading the VEVSTS0 and VEVSTS1 registers. It

should then access the register of each of the channels that has its respective bit set and clear the HIGHV and LOWV status

bits by writing 1 to each of them.

11.2.4

Power-On Reset Default States

VLM power-on default conditions are:

• All registers are loaded with their default values.

• The ALARM output, IRQ, and SMI are disabled.

11.2.5

Standby Mode

Standby mode is enabled by setting the Standby Mode Enable bit in the VLMCFG register. Standby mode reduces power

supply current by disabling new measurements, but register values are retained and the registers can be accessed by soft-

ware (as usual).

11.3 ANALOG SUPPLY CONNECTION

11.3.1

Recommendations

Power is supplied to the analog parts of the A/D Converter through two dedicated analog power pins: AVDD and AVSS. This

ensures effective isolation of the analog parts from noise caused by the digital parts. The digital parts of the VLM are supplied

via VSB. To obtain the best performance, bear in mind the following recommendations (see also details in Figure 37).

Ground Connection. The analog ground pin, AVSS, should be connected at only one point to the digital ground pins. At this

point, the following ground connections should also be made:

• The decoupling capacitors of the analog supply AV

DD pin

• The reference voltage V

REF pin

• The four digital supply V

SB pins

• The ground reference of the input signals to the A/D Converter.

Low impedance ground layers also improve noise isolation.

Power Connection. The analog supply pin, AVDD, should be connected to a low noise power supply, 3.3V. It is recommend-

ed to supply the AVDD pin through an external LC or RC filter. An example of an RC filter [R1 and (C2+C3)] is shown in

Figure 37.

Decoupling Capacitors. The following decoupling capacitors should be used:

• Digital V

SB: Place one capacitor of 0.1 µF on each VSB pin, as close as possible to the pin (4 x C4). Also, place one 10-

µF tantalum capacitor (C

5) on the common net, as close as possible to the chip.

• Analog AV

DD: Place a 0.1 µF capacitor and a 10-47 µF tantalum capacitor on the AVDD pins (C3 and C2), as close as

possible to the pin.

• V

REF: Place a low leakage, non-polarized, 0.47 µF capacitor (C1) as close as possible to the VREF pin.

PC87366 数据表(PDF) 180 Page - National Semiconductor (TI)

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