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PC87366 数据表(PDF) 188 Page - National Semiconductor (TI) |
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PC87366 数据表(HTML) 188 Page - National Semiconductor (TI) |
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188 / 240 page ![]() 11.0 Voltage Level Monitor (VLM) (Continued) 188 www.national.com 11.5.9 Voltage Conversion Rate Register (VCNVR) This register indicates time related specification for the VLM. Location: Offset 07h Type: R/W Bit 76543210 Name Reserved Channel Delay Conversion Period Reset 00000000 Bit Description 7-6 Reserved 5-3 Channel Delay. These bits define the sampling delay. The sampling delay helps guarantee the accuracy of the sampled value when switching from one channel to another. Bits 5 4 3 Delay ( µSec) 0 0 0 40 (default) 001 80 0 1 0 160 Others Reserved 2-0 Conversion Period. These bits define the period of time between reconversions of all enabled channels. VBAT (channel 9) is converted at the first of every 1024 conversion periods. Bits 2 1 0 Conversion Period 0 0 0 2 seconds (default) 0 0 1 1 second 0 1 0 0.5 seconds 0 1 1 0.1 seconds 1 0 0 0.05 seconds 1 0 1 0.02 seconds Others Reserved |
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