ST7MC1K2-Auto datasheet(152/371 Pages) STMICROELECTRONICS

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These events generate an interrupt if the corresponding enable control bit is set and the

interrupt mask in the CC register is reset (RIM instruction).

10.5.8

SCI mode registers

SCI status register (SCISR)

SCISR

Reset value: 1100 0000 (C0h)

654

TDRE

RDRF

IDLE

OR(1)

This bit has a different function in LIN mode, please refer to Section 10.5.10: LIN mode registers.

NF(1)

FE(1)

PE(1)

Table 62.

SCISR register description

Bit Name

Function

TDRE

Transmit data register empty

This bit is set by hardware when the content of the TDR register has been transferred

into the shift register. An interrupt is generated if the TIE = 1 in the SCICR2 register. It

is cleared by a software sequence (an access to the SCISR register followed by a

write to the SCIDR register).

0: Data is not transferred to the shift register

1: Data is transferred to the shift register

6TC

Transmission complete

This bit is set by hardware when transmission of a character containing data is

complete. An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by

a software sequence (an access to the SCISR register followed by a write to the

SCIDR register).

0: Transmission is not complete

1: Transmission is complete

Note: TC is not set after the transmission of a preamble or a break.

RDRF

Received data ready flag

This bit is set by hardware when the content of the RDR register has been transferred

to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 register. It is

cleared by a software sequence (an access to the SCISR register followed by a read

to the SCIDR register).

0: Data is not received

1: Received data is ready to be read

4IDLE

Idle line detected

This bit is set by hardware when an idle line is detected. An interrupt is generated if

the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to

the SCISR register followed by a read to the SCIDR register).

0: No idle line is detected

1: Idle line is detected

Note: The idle bit is not set again until the RDRF bit has been set itself (that is, a new

idle line occurs).

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