ST7MC1K2-Auto datasheet(154/371 Pages) STMICROELECTRONICS

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Table 63.

SCICR1 register description

Bit Name

Function

Receive data bit 8

This bit is used to store the 9th bit of the received word when M = 1.

6T8

Transmit data bit 8

This bit is used to store the 9th bit of the transmitted word when M = 1.

5SCID

Disabled for low power consumption

When this bit is set the SCI prescalers and outputs are stopped at the end of the

current byte transfer in order to reduce power consumption.This bit is set and cleared

by software.

0: SCI enabled

1: SCI prescaler and outputs disabled

Word length

This bit determines the word length. It is set or cleared by software.

0: 1 start bit, 8 data bits, 1 stop bit

1: 1 start bit, 9 data bits, 1 stop bit

Note: The M bit must not be modified during a data transfer (both transmission and

reception).

WAKE

Wake-up method

This bit determines the SCI wake-up method. It is set or cleared by software.

0: Idle line

1: Address mark

Note: If the LINE bit is set, the WAKE bit is deactivated and replaced by the LHDM bit.

2PCE

Parity control enable

This bit is set and cleared by software. It selects the hardware parity control

(generation and detection for byte parity, detection only for LIN parity).

0: Parity control disabled

1: Parity control enabled

1PS

Parity selection

This bit selects the odd or even parity when the parity generation/detection is enabled

(PCE bit set). It is set and cleared by software. The parity is selected after the current

byte.

0: Even parity

1: Odd parity

0PIE

Parity interrupt enable

This bit enables the interrupt capability of the hardware parity control when a parity

error is detected (PE bit set). The parity error involved can be a byte parity error (if bit

PCE is set and bit LPE is reset) or a LIN parity error (if bit PCE is set and bit LPE is

set).

0: Parity error interrupt disabled

1: Parity error interrupt enabled

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