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ST7MC1K2-Auto 数据表(PDF) 158 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 158 Page - STMicroelectronics |
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158 / 371 page  Obsolete Product(s) - Obsolete Product(s) On-chip peripherals ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto 158/371 SCI extended transmit prescaler division register (SCIETPR) 10.5.9 LIN mode - functional description The block diagram of the serial control interface, in LIN slave mode is shown in Figure 65. It uses six registers: ● 3 control registers: SCICR1, SCICR2 and SCICR3 ● 2 status registers: the SCISR register and the LHLR register mapped at the SCIERPR address ● A baud rate register: LPR mapped at the SCIBRR address and an associated fraction register LPFR mapped at the SCIETPR address The bits dedicated to LIN are located in the SCICR3. Refer to the register descriptions in Section 10.5.10: LIN mode registers for the definitions of each bit. Entering LIN mode To use the LINSCI in LIN mode the following configuration must be set in SCICR3 register: ● Clear the M bit to configure 8-bit word length. ● Set the LINE bit. Master To enter master mode the LSLV bit must be reset. In this case, setting the SBK bit sends 13 low bits. The baud rate can then be programmed using the SCIBRR, SCIERPR and SCIETPR registers. In LIN master mode, the conventional prescaler and/or extended prescaler define the baud rate (as in standard SCI mode). SCIETPR Reset value: 0000 0000 (00h) 7 654 32 10 ETPR[7:0] R/W Table 67. SCIETPR register description Bit Name Function 7:0 ETPR[7:0] 8-bit extended transmit prescaler register The extended baud rate generator is activated when a value other than 00h is stored in this register. The clock frequency from the 16 divider (see Figure 63) is divided by the binary factor set in the SCIETPR register (in the range 1 to 255). The extended baud rate generator is not active after a reset. Note: In LIN slave mode, the conventional and extended baud rate generators are disabled. Obsolete Product(s) - Obsolete Product(s) |
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