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ST7MC1K2-Auto 数据表(PDF) 155 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 155 Page - STMicroelectronics |
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155 / 371 page  Obsolete Product(s) - Obsolete Product(s) ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto On-chip peripherals 155/371 SCI control register 2 (SCICR2) SCICR2 Reset value: 0000 0000 (00h) 7 654 32 10 TIE TCIE RIE ILIE TE RE RWU(1) 1. This bit has a different function in LIN mode; please refer to Section 10.5.10: LIN mode registers. SBK(1) R/W R/W R/W R/W R/W R/W R/W R/W Table 64. SCICR2 register description Bit Name Function 7 TIE Transmitter interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register 6TCIE Transmission complete interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TC = 1 in the SCISR register 5RIE Receiver interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR register 4ILIE Idle line interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register 3TE Transmitter enable This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled Notes: - During transmission, a ‘0’ pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble (idle line) after the current word. - When TE is set there is a 1 bit-time delay before the transmission starts. 2RE Receiver enable This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled in the SCISR register 1: Receiver is enabled and begins searching for a start bit Obsolete Product(s) - Obsolete Product(s) |
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