ST7MC1K2-Auto datasheet(157/371 Pages) STMICROELECTRONICS

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SCI extended receive prescaler division register (SCIERPR)

Table 65.

SCIBRR register description

Bit

Name

Function

7:6 SCP[1:0]

First SCI prescaler

These 2 prescaling bits allow several standard clock division ranges:

00: PR prescaling factor = 1

01: PR prescaling factor = 3

10: PR prescaling factor = 4

11: PR prescaling factor = 13

5:3 SCT[2:0]

SCI transmitter rate divisor

These 3 bits, in conjunction with the SCP1 and SCP0 bits define the total division

applied to the bus clock to yield the transmit rate clock in conventional baud rate

generator mode:

000: TR dividing factor = 1

001: TR dividing factor = 2

010: TR dividing factor = 4

011: TR dividing factor = 8

100: TR dividing factor = 16

101: TR dividing factor = 32

110: TR dividing factor = 64

111: TR dividing factor = 128

2:0 SCR[2:0]

SCI receiver rate divider

These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied

to the bus clock to yield the receive rate clock in conventional baud rate generator

mode:

000: RR dividing factor = 1

001: RR dividing factor = 2

010: RR dividing factor = 4

011: RR dividing factor = 8

100: RR dividing factor = 16

101: RR dividing factor = 32

110: RR dividing factor = 64

111: RR dividing factor = 128

SCIERPR

Reset value: 0000 0000 (00h)

654

ERPR[7:0]

R/W

Table 66.

SCIERPR register description

Bit

Name

Function

7:0 ERPR[7:0]

8-bit extended receive prescaler register

The extended baud rate generator is activated when a value other than 00h is

stored in this register. The clock frequency from the 16 divider (see Figure 63) is

divided by the binary factor set in the SCIERPR register (in the range 1 to 255).

The extended baud rate generator is not active after a reset.

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