LPC802 datasheet(17/83 Pages) NXP

17 / 83 page

LPC802

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Product data sheet

Rev. 1.6 — 27 April 2018

17 of 83

NXP Semiconductors

LPC802

32-bit ARM Cortex-M0+ microcontroller

9.6 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0+. The tight

coupling to the CPU allows for low interrupt latency and efficient processing of late arriving

interrupts.

9.6.1 Features

• Nested Vectored Interrupt Controller is a part of the ARM Cortex-M0+.

• Tightly coupled interrupt controller provides low interrupt latency.

• Controls system exceptions and peripheral interrupts.

• Supports 32 vectored interrupts.

• In the LPC802, the NVIC supports vectored interrupts for each of the peripherals and

the eight pin interrupts.

• Four programmable interrupt priority levels with hardware priority level masking.

• Software interrupt generation using the ARM exceptions SVCall and PendSV.

• Supports NMI.

9.6.2 Interrupt sources

Each peripheral device has at least one interrupt line connected to the NVIC but can have

several interrupt flags. Individual interrupt flags can also represent more than one interrupt

source.

9.7 System tick timer

The ARM Cortex-M0+ includes a 24-bit system tick timer (SysTick) that is intended to

generate a dedicated SysTick exception at a fixed time interval (typically 10 ms).

9.8 I/O configuration

The IOCON block controls the configuration of the I/O pins. Each digital or mixed

digital/analog pin with the PIO0_n designator in Table 4 can be configured as follows:

• Enable or disable the weak internal pull-up and pull-down resistors.

• Select a pseudo open-drain mode. The input cannot be pulled up above VDD. The

pins are not 5 V tolerant when VDD is grounded.

• Program the input glitch filter with different filter constants using one of the IOCON

divided clock signals (IOCONCLKCDIV, see Figure 12 “LPC802 clock generation”).

You can also bypass the glitch filter.

• Invert the input signal.

• Hysteresis can be enabled or disabled.

• The switch matrix setting enables the analog input mode on pins with analog and

digital functions. Enabling the analog mode disconnects the digital functionality.

• The LPC802 uses a dual voltage I/O feature. The pins on one side of the package are

supplied by VDDIO and the pins on the other side are supplied by VDD. Each of these

two supplies can be connected to different voltages within the allowed Vdd range.

This feature allows the device to level-shift signals from one off-chip voltage domain to

another.

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