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LPC802 数据表(PDF) 27 Page - NXP Semiconductors |
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LPC802 数据表(HTML) 27 Page - NXP Semiconductors |
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27 / 83 page ![]() LPC802 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 1.6 — 27 April 2018 27 of 83 NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 9.22 Clocking and power control Fig 12. LPC802 clock generation aaa-027119 fro clk_in lposc_clk fro_div Main clock select MAINCLKSEL[1:0] 00 01 10 (1) 11 SYSAHBCLKDIV SYSAHBCLKCTRL (one bit per destination) main_clk main_clk Divider to AHB peripherals, AHB matrix, memories, etc. to CPU CLKOUTDIV CLKOUT Divider fro clk_in “none” ADC clock select ADCCLKSEL[1:0] 00 01 11 ADCCLKDIV ADC Clock Divider to ADC fro (1) : synchronized multiplexer, see register desriptions for details. main_clk clk_in CLKOUT select CLKOUTSEL[2:0] 001 100 000 011 lposc_clk 111 “none” CLKOUT 010 “none” |
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