LPC802 datasheet(13/83 Pages) NXP

13 / 83 page

LPC802

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.6 — 27 April 2018

13 of 83

NXP Semiconductors

LPC802

32-bit ARM Cortex-M0+ microcontroller

[1]

Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD

level); IA = inactive, no pull-up/down enabled; F = floating. For pin states in the different power modes, see Section 15.5 “Pin states in

different power modes”. For termination on unused pins, see Section 15.4 “Termination of unused pins”.

[2]

5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When

configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.

[3]

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes

high-current output driver.

[4]

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

[5]

See Figure 16 for the reset pad configuration. This pin includes a 20 ns glitch filter (active in all power modes). RESET functionality is

not available in deep power-down mode. Use the WAKEUP pins to reset the chip and wake up from deep power-down mode.

[6]

The WKTCLKIN function is enabled in the PINENABLE0 register in the PMU. See the LPC802 user manual.

[7]

The digital part of this pin is 3 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with

configurable modes, configurable hysteresis, and an analog input. When configured as an analog input, the digital section of the pin is

disabled.

[8]

Thermal pad for HVQFN33.

VDD

If VDDIO is present, VDD is the supply voltage

for the I/Os on the right side of the package

and the core voltage regulator. If VDDIO is not

present, VDD also supplies voltage to the I/Os

on the left side of the package.

VDDIO

If present, it is the supply voltage for the I/Os

on the left side of the package.

VSS

33[8]

Ground.

VREFP

181523

VREFP — ADC positive reference voltage.

Must be equal or lower than VDD.

n.c.

10,

11,

12,

13,

14,

15,

21,

26,

27,

28,

29,

30,

no connect.

Table 4.

Pin description

Symbol

Reset

state[1]

Type

Description

LPC802 数据表(PDF) 13 Page - NXP Semiconductors

LPC802 数据表(HTML) 13 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

数据表下载