LPC802 datasheet(19/83 Pages) NXP

19 / 83 page

LPC802

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Product data sheet

Rev. 1.6 — 27 April 2018

19 of 83

NXP Semiconductors

LPC802

32-bit ARM Cortex-M0+ microcontroller

9.9 Switch Matrix (SWM)

The switch matrix controls the function of each digital or mixed analog/digital pin in a

highly flexible way by allowing to connect many functions like the USART, SPI, CTimer,

and I2C functions to any pin that is not power or ground. These functions are called

movable functions and are listed in Table 5.

Functions that need specialized pads can be enabled or disabled through the switch

matrix. These functions are called fixed-pin functions and cannot move to other pins. The

fixed-pin functions are listed in Section 7.2 “Pin description”. If a fixed-pin function is

disabled, any other movable function can be assigned to this pin.

9.10 Fast General-Purpose parallel I/O (GPIO)

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs

can be set or cleared in one write operation.

LPC802 use accelerated GPIO functions:

• GPIO registers are on the ARM Cortex-M0+ IO bus for fastest possible single-cycle

I/O timing, allowing GPIO toggling with rates of up to 7 MHz.

• An entire port value can be written in one instruction.

• Mask, set, and clear operations are supported for the entire port.

All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the

switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be

moved to another pin. Except for pins SWDIO/PIO0_2, SWCLK/PIO0_3, and

RESET/PIO0_5, the switch matrix enables the GPIO port pin function by default.

9.10.1 Features

• Bit level port registers allow a single instruction to set and clear any number of bits in

one write operation.

• Direction control of individual bits.

• All I/O default to GPIO inputs with internal pull-up resistors enabled after reset.

• Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed

through the IOCON block for each GPIO pin (see Figure 10).

• Direction (input/output) can be set and cleared individually.

• Pin direction bits can be toggled.

9.11 Pin interrupt

The pin interrupt block configures up to eight pins from all digital pins for providing eight

external interrupts connected to the NVIC.

Any digital pin, independently of the function selected through the switch matrix, can be

configured through the SYSCON block as input to the pin interrupt. The registers that

control the pin interrupt are on the IO+ bus for fast single-cycle access.

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