LPC802 datasheet(53/83 Pages) NXP

53 / 83 page

LPC802

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Product data sheet

Rev. 1.6 — 27 April 2018

53 of 83

NXP Semiconductors

LPC802

32-bit ARM Cortex-M0+ microcontroller

13.6 SPI interfaces

The actual SPI bit rate depends on the delays introduced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by external device and PCB, the maximum supported bit rate for SPI master

mode is 15 Mbit/s, and the maximum supported bit rate for SPI slave mode is 1/(2 x 28 ns)

= 17.8 Mbit/s at 3.0v <= VDD <= 3.6v and 1/(2 x 32 ns) = 15.6 Mbit/s at 1.7v <= VDD <=

3.0v.

Remark: SPI functions can be assigned to all digital pins. The characteristics are valid for

all digital pins.

Table 21.

SPI dynamic characteristics

Tamb = 40 C to 105 C; CL = 20 pF; input slew = 1 ns. Simulated parameters sampled at the 30 %

and 70 % level of the rising or falling edge; values guaranteed by design. Delays introduced by the

external trace or external device are not considered.

Symbol

Parameter

Conditions

Min

Max

Unit

SPI master

tDS

data set-up time

1.71 V <= VDD <= 3.6 V

tDH

data hold time

1.71 V <= VDD <= 3.6 V

tv(Q)

data output valid time

1.71 V <= VDD <= 3.6 V

SPI slave

tDS

data set-up time

1.71 V <= VDD <= 3.6 V

tDH

data hold time

1.71 V <= VDD <= 3.6 V

tv(Q)

data output valid time

3.0 V <= VDD <= 3.6 V

1.71 V <= VDD < 3.0 V

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