LPC802 datasheet(31/83 Pages) NXP

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LPC802

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Product data sheet

Rev. 1.6 — 27 April 2018

31 of 83

NXP Semiconductors

LPC802

32-bit ARM Cortex-M0+ microcontroller

9.22.4 Power control

The LPC802 supports the ARM Cortex-M0+ sleep mode. The CPU clock rate may also be

controlled as needed by changing clock sources, and/or altering the CPU clock divider

value. This allows a trade-off of power versus processing speed based on application

requirements. In addition, a register is provided for shutting down the clocks to individual

on-chip peripherals, allowing to fine-tune power consumption by eliminating all dynamic

power use in any peripherals that are not required for the application. Selected

peripherals have their own clock divider which provides even better power control.

9.22.4.1 Sleep mode

When sleep mode is entered, the clock to the core is stopped. Resumption from the sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

In sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during sleep mode and may generate

interrupts to cause the processor to resume execution. sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

9.22.4.2 Deep-sleep mode

In deep-sleep mode, the LPC802 core is in sleep mode and all peripheral clocks and all

clock sources are off except for the FRO or low-power oscillator if selected. The FRO

output is disabled. In addition, all analog blocks are shut down and the flash is in standby

mode. In deep-sleep mode, the application can keep the low power oscillator and the

BOD circuit running for self-timed wakeup and BOD protection.

The LPC802 can wake up from deep-sleep mode via a reset, digital pins selected as

inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the

USART (if the USART is configured in synchronous slave mode), the SPI (in slave mode),

or the I2C blocks (in slave mode).

Any interrupt used for waking up from deep-sleep mode must be enabled in one of the

SYSCON wake-up enable registers and the NVIC.

Deep-sleep mode saves power and allows for short wake-up times.

9.22.4.3 Power-down mode

In power-down mode, the LPC802 is in sleep mode and all peripheral clocks and all clock

sources are off except for low-power oscillator if selected. In addition, all analog blocks

and the flash are shut down. In power-down mode, the application can keep the

low-power oscillator and the BOD circuit running for self-timed wake up and BOD

protection.

The LPC802 can wake up from power-down mode via a reset, digital pins selected as

inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the

USART (if the USART is configured in synchronous slave mode), the SPI (in slave mode),

or the I2C blocks (in slave mode).

Any interrupt used for waking up from power-down mode must be enabled in one of the

SYSCON wake-up enable registers and the NVIC.

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