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LPC802 数据表(PDF) 58 Page - NXP Semiconductors |
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LPC802 数据表(HTML) 58 Page - NXP Semiconductors |
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58 / 83 page ![]() LPC802 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 1.6 — 27 April 2018 58 of 83 NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 14.2 ADC [1] The input resistance of ADC channel 0 is higher than for all other channels. See Figure 30. [2] In the ADC TRM register, set VRANGE = 0 (default). [3] In the ADC TRM register, set VRANGE = 1 (default). [4] Based on characterization. Not tested in production. [5] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 30. [6] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 30. [7] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 30. [8] The full-scale error voltage or gain error (EG) is the difference between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 30. [9] Tamb = 25 C; maximum sampling frequency fs = 480 Ksamples/s and analog input capacitance Cia = 26 pF. [10] Input impedance Zi (see Section 14.2.1) is inversely proportional to the sampling frequency and the total input capacity including Cia and Cio: Zi 1 / (fs Ci). See Table 12 for Cio. Table 25. 12-bit ADC static characteristics Tamb = 40 C to +105 C unless noted otherwise; VDD = 2.5 V to 3.6 V; VREFP = VDD; VREFN = VSS. Symbol Parameter Conditions Min Typ Max Unit VIA analog input voltage 0 - VDD V Vref reference voltage on pin VREFP 2.5 - VDD V Cia analog input capacitance - - 26 pF fclk(ADC) ADC clock frequency [2] -- 15 MHz fs sampling frequency [2] - - 480 Ksamples/s ED differential linearity error [5][4] - 1- LSB EL(adj) integral non-linearity [6][4] - 4- LSB EO offset error [7][4] - 3- LSB Verr(fs) full-scale error voltage [8][4] -0.1 - % Zi input impedance fs = 480 Ksamples/s [1][9] [10] 0.1 - - M |
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