LPC802 datasheet(79/83 Pages) NXP

79 / 83 page

LPC802

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.6 — 27 April 2018

79 of 83

NXP Semiconductors

LPC802

32-bit ARM Cortex-M0+ microcontroller

20. Revision history

Table 34.

Revision history

Document ID

Release date

Data sheet status

Change notice Supersedes

LPC802 v.1.6

20180427

Product data sheet

LPC802 v.1.5

Modifications:

• Added LPC802UK part.

• Added text to Section 9.22.4.4 “Deep power-down mode”: Five general-purpose

registers are available to store information during deep power-down mode.

• Updated Section 9.22.1 “Internal oscillators”. Changed heading title.

• Updated Section 15.2 “Connecting power, clocks, and debug functions”: removed text:

connect the external crystal.

LPC802 v.1.5

20180312

Product data sheet

LPC802 v.1.4

Modifications:

• Updated Table 3 “Device revision table”.

LPC802 v.1.4

20180227

Product data sheet

LPC802 v.1.3

Modifications:

• Added Figure 38 “Package outline WLCSP16 (1.86 ´1.86 ´ 0.3 mm)”.

• Added Figure 42 “Reflow soldering for the WLCSP16 (4x4) package (1 of 3)”, Figure

43 “Reflow soldering for the WLCSP16 (4x4) package (2 of 3)”, and Figure 44 “Reflow

soldering for the WLCSP16 (4x4) package (3 of 3)”.

• Updated title of Section 13.1 “Flash memory (EEPROM based)”.

• Updated Table 12 “Static characteristics, supply pins”: Added condition: system clock

= 1 MHz, VDD = 3.3 V.

• Updated Table 16 “Dynamic characteristic: FRO”: Max values: FRO clock frequency;

Condition:

20 C  Tamb  70 C and FRO clock frequency; Condition: 40 C  Tamb

 105 C.

LPC802 v.1.3

20180209

Product data sheet

LPC802 v.1.2

Modifications:

• Updated Section 2 “Features and benefits”.

• Updated Table 5 “Movable functions (assign to pins PIO0_0 to PIO0_5, PIO0_7 to

PIO0_17 through switch matrix)”.

• Added level shifter functionality to Section 9.8 “I/O configuration”.

• Updated Table 16 “Dynamic characteristic: FRO”: Changed frequencies to 9 MHz, 12

MHz, and 15 MHz. Added Condition:

20 C  Tamb  70 C and Condition: 40 C 

Tamb  70 C.

LPC802 v.1.2

20171222

Product data sheet

LPC802 v.1.1

Modifications:

• Updated Figure 4 “LPC802 block diagram”.

• Updated Figure 12 “LPC802 clock generation”.

• Updated Table 7 “Peripheral configuration in reduced power modes”: In deep-sleep

mode flash is on standby.

LPC802 v.1.1

20171222

Product data sheet

LPC802 v.1

Modifications:

• Updated Figure 21 “High-drive output: Typical HIGH-level output voltage VOH versus

HIGH-level output current IOH” at 1.8 V.

LPC802 v.1

20171218

Product data sheet

LPC802 数据表(PDF) 79 Page - NXP Semiconductors

LPC802 数据表(HTML) 79 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

数据表下载

链接网址

LPC802 数据表(PDF) 79 Page - NXP Semiconductors

LPC802 数据表(HTML) 79 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

数据表 下载

链接网址

数据表下载