LPC802 datasheet(30/83 Pages) NXP

30 / 83 page

LPC802

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Product data sheet

Rev. 1.6 — 27 April 2018

30 of 83

NXP Semiconductors

LPC802

32-bit ARM Cortex-M0+ microcontroller

9.22.1 Internal oscillators

The LPC802 include two independent oscillators:

1. Free Running Oscillator.

2. Low power oscillator.

Following reset, the LPC802 operates from the FRO until switched by software allowing

the part to run without any external clock and the bootloader code to operate at a known

frequency.

See Figure 12 for an overview of the LPC802 clock generation.

9.22.1.1 Free Running Oscillator (FRO)

The FRO provides the default clock at reset and provides a clean system clock shortly

after the supply pins reach operating voltage.

• This oscillator provides a selectable 15 MHz, 12 MHz, and 9 MHz outputs that can be

used as a system clock. Also, these outputs can be divided down to 7.5 MHz, 6 MHz,

and 4.5 MHz for system clock.

• The FRO is trimmed to ±1 % accuracy over the entire voltage and temperature range

of 0 C to 70 C.

• By default, the FRO output frequency is default system (CPU) clock frequency of 12

MHz.

9.22.1.2 Low Power Oscillator (LPOsc)

The LPOsc is an independent oscillator which can be used as a system clock. The

frequency of the LPCOsc is 1 MHz.

9.22.2 Clock input

An external clock source can be supplied on the selected CLKIN pin. When selecting a

clock signal for the CLKIN pin, follow the specifications for digital I/O pins in Table 12

“Static characteristics, supply pins” and Table 18 “Dynamic characteristics: I/O pins[1]”.

The maximum frequency for both clock signals is 15 MHz.

9.22.3 Clock output

The LPC802 features a clock output function that routes any oscillator or the main clock

can be selected to the CLKOUT function. The CLKOUT function can be connected to any

digital pin through the switch matrix.

main_clk

The main clock used by the CPU and AHB bus, and potentially many others. The main clock and its source

selection are shown in Figure 12.

“none”

A tied-off source that should be selected to save power when the output of the related multiplexer is not

used.

lposc_clk

The output of the 1 MHz low power oscillator. It must also be enabled in the PDRUNCFG0 register.

Table 6.

Clocking diagram signal name descriptions

Name

Description

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