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LPC802 数据表(PDF) 32 Page - NXP Semiconductors

部件名 LPC802
功能描述  32-bit ARM Cortex-M0 microcontroller
PDF  83 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

LPC802 数据表(HTML) 32 Page - NXP Semiconductors

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LPC802
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.6 — 27 April 2018
32 of 83
NXP Semiconductors
LPC802
32-bit ARM Cortex-M0+ microcontroller
Power-down mode reduces power consumption compared to deep-sleep mode at the
expense of longer wake-up times.
9.22.4.4 Deep power-down mode
In deep power-down mode, power is shut off to the entire chip except for the WAKEUP
pins. The LPC802 can wake up from deep power-down mode via eight WAKEUP pins.
See Section 9.18. Five general-purpose registers are available to store information during
deep power-down mode.
The LPC802 can be prevented from entering deep power-down mode by setting a lock bit
in the PMU block. Locking out deep power-down mode enables the application to keep
the watchdog timer or the BOD running at all times.
When entering deep power-down mode, an external pull-up resistor is required on the
WAKEUP pins to hold it HIGH.
Table 7.
Peripheral configuration in reduced power modes
Peripheral
Sleep mode
Deep-sleep mode
Power-down mode
Deep power-down
mode
FRO
software configurable
on
off
off
FRO output
software configurable
off
off
off
Flash
software configurable
standby
off
off
BOD
software configurable
software configurable
software configurable off
LPOsc/WWDT
software configurable
software configurable
software configurable off
Digital peripherals software configurable
off
off
off
Wake-up buffers
software configurable (cannot
be used as wake-up source)
software configurable
(cannot be used as
wake-up source)
software configurable
(cannot be used as
wake-up source)
software configurable
ADC
software configurable
off
off
off



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