LPC802 datasheet(22/83 Pages) NXP

22 / 83 page

LPC802

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Product data sheet

Rev. 1.6 — 27 April 2018

22 of 83

NXP Semiconductors

LPC802

32-bit ARM Cortex-M0+ microcontroller

• Counter or timer operation.

• Up to three 32-bit captures can take a snapshot of the timer value when an input

signal transitions. A capture event may also optionally generate an interrupt. The

number of capture inputs for each timer that are actually available on device pins can

vary by device.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

– Shadow registers are added for glitch-free PWM output.

• For each timer, up to 4 external outputs corresponding to match registers with the

following capabilities (the number of match outputs for each timer that are actually

available on device pins can vary by device):

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

• The timer and prescaler may be configured to be cleared on a designated capture

event. This feature permits easy pulse width measurement by clearing the timer on

the leading edge of an input pulse and capturing the timer value on the trailing edge.

• Up to 4 match registers can be configured for PWM operation, allowing up to 3 single

edged controlled PWM outputs. (The number of match outputs for each timer that are

actually available on device pins can vary by device.)

9.16 Multi-Rate Timer (MRT)

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with two channels. Each

channel can be programmed with an independent time interval, and each channel

operates independently from the other channels.

9.16.1 Features

• 31-bit interrupt timer

• Two channels independently counting down from individually set values

• Bus stall, repeat and one-shot interrupt modes

9.17 Windowed WatchDog Timer (WWDT)

The watchdog timer resets the controller if software fails to service the watchdog timer

periodically within a programmable time window.

9.17.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out

period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

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