LPC802 datasheet(57/83 Pages) NXP

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LPC802

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Product data sheet

Rev. 1.6 — 27 April 2018

57 of 83

NXP Semiconductors

LPC802

32-bit ARM Cortex-M0+ microcontroller

13.8 Wake-up process

[1]

Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply

voltages.

[2]

The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up

from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR)

wake-up handler. ISR is located in SRAM.

[3]

FRO enabled, all peripherals off.

[4]

Wake up from deep power-down causes the part to go through entire reset

process. The wake-up time measured is the time between when the Wake-Up pin is triggered to wake the

device up and when a GPIO output pin is set in the reset handler.

14. Characteristics of analog peripherals

14.1 BOD

[1]

Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see the

LPC802 user manual.

Table 23.

Dynamic characteristic: Typical wake-up times from low power modes

VDD = 3.3 V;Tamb =25 C; Using FRO (15 MHz) as the system clock.

Symbol Parameter

Conditions

Min

Typ[1]

Max Unit

twake

wake-up

time

from sleep mode

[2][3] -1.97

s

from deep-sleep mode

[2] -2.07

s

from power-down mode

[2] -25

s

from deep power-down mode

[4] -313

s

Table 24.

BOD static characteristics[1]

Tamb =25 C.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Vth

threshold voltage

interrupt level 1

assertion

2.24

de-assertion

2.40

interrupt level 2

assertion

2.52

de-assertion

2.64

interrupt level 3

assertion

2.81

de-assertion

2.90

reset level 0

assertion

1.51

de-assertion

1.54

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