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LPC802 数据表(PDF) 20 Page - NXP Semiconductors |
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LPC802 数据表(HTML) 20 Page - NXP Semiconductors |
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20 / 83 page ![]() LPC802 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 1.6 — 27 April 2018 20 of 83 NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 9.11.1 Features • Pin interrupts – Up to eight pins can be selected from all digital pins as edge- or level-sensitive interrupt requests. Each request creates a separate interrupt in the NVIC. – Edge-sensitive interrupt pins can interrupt on rising or falling edges or both. – Level-sensitive interrupt pins can be HIGH- or LOW-active. – Pin interrupts can wake up the LPC802 from sleep mode, deep-sleep mode, and power-down mode. 9.12 USART0/1 All USART functions are movable functions and are assigned to pins through the switch matrix. 9.12.1 Features • Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous mode for USART functions connected to all digital pins. • 7, 8, or 9 data bits and 1 or 2 stop bits • Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option. • Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485 possible with software address detection and transceiver direction control.) • Parity generation and checking: odd, even, or none. • One transmit and one receive data buffer. • RTS/CTS for hardware signaling for automatic flow control. Software flow control can be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an RTS output. • Received data and status can optionally be read from a single register • Break generation and detection. • Receive data is 2 of 3 sample "voting". Status flag set when one sample differs. • Built-in Baud Rate Generator. • A fractional rate divider is shared among all UARTs. • Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS detect, and receiver sample noise detected. • Separate data and flow control loopback modes for testing. • Baud rate clock can also be output in asynchronous mode. 9.13 SPI0 All SPI functions are movable functions and are assigned to pins through the switch matrix. |
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