LPC802 datasheet(7/83 Pages) NXP

7 / 83 page

LPC802

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.6 — 27 April 2018

7 of 83

NXP Semiconductors

LPC802

32-bit ARM Cortex-M0+ microcontroller

6. Block diagram

Fig 4.

LPC802 block diagram

aaa-028309

CLKOUT

Vdd

CLKIN

ISP Access Port

RESET

Clock Generation,

Power Control,

and other

System Functions

Voltage Regulator

DEBUG

INTERFACE

IOP bus

GPIOs

GPIOs AND

GPOINT

Flash

interface

Flash

16 kB

Multilayer

AHB Matrix

AHB to

APB bridge

T0 Match/

Capture

COMP

Inputs

ADC inputs

and Triggers

GPIOs

UART0,1

SPI0

I2C0

APB slave group

LPOSc

Windowed WDT

ARM

Cortex M0+

System control

IOCON Registers

CTIMER0

UART 0 and 1

SPI0

I2C 0

Periph Input Mux Selects

Comparator

PMU Registers

12-bit ADC

Switch Matrix

Wakeup Timer

Multi-Rate Timer

Boot ROM

8 kB

SRAM

2 kB

LPC802 数据表(PDF) 7 Page - NXP Semiconductors

LPC802 数据表(HTML) 7 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

数据表下载