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LPC802 数据表(PDF) 1 Page - NXP Semiconductors |
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LPC802 数据表(HTML) 1 Page - NXP Semiconductors |
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1 / 83 page  1. General description The LPC802 are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 15 MHz. The LPC802 supports 16 KB of flash memory and 2 KB of SRAM. The peripheral complement of the LPC802 includes one I2C-bus interface, up to two USARTs, one SPI interface, one multi-rate timer, self-wake-up timer, one general purpose 32-bit counter/timer, one 12-bit ADC, one analog comparator, function-configurable I/O ports through a switch matrix, and up to 17 general-purpose I/O pins. For additional documentation related to the LPC802 parts, see Section 19. 2. Features and benefits System: ARM Cortex-M0+ processor (revision r0p1), running at frequencies of up to 15 MHz with single-cycle multiplier and fast single-cycle I/O port. ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC). System tick timer. AHB multilayer matrix. Serial Wire Debug (SWD) with four break points and two watch points. JTAG boundary scan (BSDL) supported. Memory: 16 KB on-chip EEPROM based flash programming memory. Code Read Protection (CRP). 2 KB SRAM. Dual I/O power (LPC802M011JDH20): Independent supplies on each package side permitting level-shifting signals from one off-chip voltage domain to another and/or interfacing directly to off-chip peripherals operating at different supply levels. The switch matrix provides level shifter functionality to allow up to two selected signals to be routed from user-selected pins in one voltage domain to selected pins in the alternate domain. This feature can also be used on a single supply device if voltage level shifting is not required. ROM API support: Boot loader. Supports Flash In-Application Programming (IAP). Supports In-System Programming (ISP) through USART. LPC802 32-bit ARM Cortex-M0+ microcontroller; up to 16 KB flash and 2 KB SRAM; 12-bit ADC; Comparator; Rev. 1.6 — 27 April 2018 Product data sheet |
类似零件编号 - LPC802 |
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类似说明 - LPC802 |
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