| 数据搜索系统,热门电子元器件搜索 |
|
EM6812F2TP24B 数据表(PDF) 41 Page - EM Microelectronic - MARIN SA |
|
|
|||||||||||||||||||||||||||||
EM6812F2TP24B 数据表(HTML) 41 Page - EM Microelectronic - MARIN SA |
|
41 / 81 page ![]() R EM6812 Copyright © 2005, EM Microelectronic-Marin SA 41 www.emmicroelectronic.com 10.3.5 Don’t care bits A don’t care function is provided so that the input status is only taken into account if the corresponding mask selection bit is set. Special: If all relevant bits of a function are set as ‘don’t care’, then this function is inhibited. 10.3.6 Debouncer The Reset and the Wake-Up signal have a debouncer selection with either a fast or low speed clock. If the debouncer is selected, the corresponding input signal must remain stable during 1 full debouncer clock period to pass. In sleep mode (no clock) the debouncer is automatically by-passed. The debouncer clock is coming from the prescaler1, and either Pr1ck[8] (256Hz) or Pr1ck[13] (8kHz) can be selected with CkDebWk for wake-up and CkDebRes for the reset function. Note: To avoid detection spikes on input or mask changes it is strongly encouraged to always selecting the debouncer functionality. 10.4 Oscillation Loop On pad terminals PA[6] (RCOut) and PA[4] (RCIn) a simple oscillation system can be made using external components (i.e. RC oscillator with resistor from, PA[6] to PA[4] and capacitor from PA[4] to VSS). The Oscillation loop is configured with the bit RCLoop in RegCfgPA. With RCLoop set the inverted PA[4] input value is output on PA[6]. The input schmitt-trigger levels give the oscillation signal on PA[4]. For correct operation PA[6] needs to be configured as output and PA[4] as input. Refer to Table 32. Port A IO mode. Figure 23. Port A oscillation loop 10.4.1 Inverter function The RC oscillation loop can also be used as a signal inverter. Any signal connected to PA[4] will be feed out inverted on PA[6] if the RCLoop bit is set. 10.5 Dual Port RAM interface The control signals and addresses for the embedded dual port RAM are mapped on port A. Refer to Table 29. Port A External Connectivity. The involved port A terminals must be set in input mode. Pull selection will be active as specified in Table 32. Port A IO mode. Please refer to chapter 5.3 Dual Port Ram for a full description. Rext Cext 0 1 PAIOSel[6] RCLoop OutPA[6] PAIn[4] PA [4] PA [6] internal external Input low threshold Input high threshold PA [6] PA [4] PA[4], PA[6] Signal flow |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |