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EM6812F2TP24B 数据表(PDF) 66 Page - EM Microelectronic - MARIN SA

部件名 EM6812F2TP24B
功能描述  Ultra Low Power 8-bit FLASH Microcontroller
PDF  81 Pages
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制造商  EMMICRO [EM Microelectronic - MARIN SA]
网页  http://www.emmicroelectronic.com
标志 EMMICRO - EM Microelectronic - MARIN SA

EM6812F2TP24B 数据表(HTML) 66 Page - EM Microelectronic - MARIN SA

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EM6812
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14.2
Interrupt acquisition
A positive edge on any of the unmasked interrupt source signals will set the corresponding interrupt register bit and activate
the mapped CPU interrupt input. (I.e. Timer3 interrupt will set bit Int2[2] in register RegInt20 and activate the CPUInt2
interrupt input if mask bit Msk2[2] is ‘1’). The 3 priority branches for interrupt acquisition are totally independent of each
other, masking and selective clear of interrupts on one interrupt vector input does not modify the others. Please refer also to
Figure 38, Interrupt acquisition architecture.
Table 57. Interrupts signal sources and destination
Priority
mapping
Interrupt source
signal from the
periphery
Interrupt
request
register bits
Interrupt mask
register bits
Mapped on CPU Interrupt input
(OR-function)
Pr1Ck[7]
Int0[3]
Msk0[3]
Pr1Ck[5]
Int0[2]
Msk0[2]
Pr1Ck[0]
Int0[1]
Msk0[1]
0
(high)
PM_miss_skip
Int0[0]
Msk0[0]
CPUInt0
Interrupt source from register RegInt00
Interrupt masking in register RegMsk00
1
(medium)
IrqPA[7:0]
Int1[7:0]
Msk1[7:0]
CPUInt1
Interrupt source from register RegInt10
Interrupt masking in register RegMsk10
IrqDR[1:0]
Int2[7:6]
Msk2[7:6]
IrqSPI[1:0]
Int2[5:4]
Msk2[5:4]
IrqTimer4
Int2[3]
Msk2[3]
IrqTimer3
Int2[2]
Msk2[2]
IrqTimer2
Int2[1]
Msk2[1]
2
(low)
IrqTimer1
Int2[0]
Msk2[0]
CPUInt2
Interrupt source from register RegInt20
Interrupt masking in register RegMsk20
Figure 38, Interrupt acquisition architecture
Q
Q
SET
CLR
D
End of Int 2 read
Write ‘0’ to Int2[n]
ResSys
Int2[7:0]
8
8
8
IrqDR[1]
IrqDR[0]
IrqSPI[1]
IrqSPI[0]
Irq Timer4
Irq Timer3
Irq Timer2
Irq Timer1
CPUInt2
8
0
1
2
3
4
5
6
7
Q
Q
SET
CLR
D
Msk1[7:0]
End of Int 1 read
Write ‘0’ to Int1[n]
ResSys
Int1[7:0]
8
8
8
PAIrq[7]
PAIrq[6]
PAIrq[5]
PAIrq[4]
PAIrq[3]
PAIrq[2]
PAIrq[1]
PAIrq[0]
CPUInt1
8
0
1
2
3
4
5
6
7
Msk2[7:0]
Q
Q
SET
CLR
D
End of Int 0 read
Write ‘0’ to Int0[n]
ResSys
Int0[3:0]
Pr1Ck[7]
Pr1Ck[5]
Pr1Ck[0]
PM_miss_skip
CPUInt0
4
4
4
4
0
1
2
3
Msk0[3:0]



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