EM6812F2TP24B datasheet(19/81 Pages) EMMICRO

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EM6812

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RegWDKey

0x3C

Watchdog key register

Bit

Name

Res

Reset by

R/W

Description

7-0

WDKey

ResSys

R*/W

WD key word to allow the software disabling the

watchdog if = ‘10010110’ bin

R*: The WDkey bits always read '00' if no valid WDKey or if WDKeyLock is locked

RegAnaCfg

0x20

BrownOut and SVLD handling

Bit

Name

Res

Reset by

R/W

Description

EnSvld

ResSys

R/W

Enable the SVLD function

EnBrownOut

POR

R/W

Enable the Brownout function

SvldLevel1

ResSys

SvldLevel2

ResSys

SvldLevel3

ResSys

SVLD level selection (1 out of 8 levels)

SVLDStatus

Svld result ‘0’ = VDD > SVLD Level

‘1’ = VDD < SVLD Level

7.2

POR and PowerCheck

At power-up the POR initializes the whole circuit and enables the power check function. The POR signal remains active

and keeps until the supply voltage is above VPOR (~1.5V). The CPU is held in reset state until power supply reaches the

power check level voltage VPWC (~2.05V) but at minimum arround 10ms after POR releasing. Power Check is eliminating

the grey zone between VPOR and VDDmin (2.0V) by releasing system operation not before the minimal specified supply

voltage is reached.

The POR cell supervises the regulated voltage observable on VREG terminal. Vreg is also the supply voltage for the whole

peripheral logic including the CPU core. The Voltage regulator output impedance together with the external capacitor on

VREG terminal form a low pass filter which protect the core logic and the POR cell from noisy power supplies. Pulling

VREG below VPOR voltage will also trigger a POR event and putting the circuit in reset state.

Figure 9. POR and Power Check behavior

1: Power up phase, power on reset and Power check switched on

2: Noise on VDD filtered on Vreg

3: Large and long drop on VDD, Vreg terminal falls below VPOR voltage. POR and power check initiated.

4: Large but short drop in VDD voltage. Vreg filter prevents to initiate POR.

VDDmin

POR

VPWC

PWR Check

VDD

VREG

[V]

time

VPOR

1.5V

2.0V

2.05

T1 is minimum around 10ms

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