EM6812F2TP24B datasheet(27/81 Pages) EMMICRO

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EM6812

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8.3.2

Low frequency external clock

The low frequency external clock coming from OscOut terminal is used to replace the Xtal oscillator. SelExtLFck in

RegSys2 controls the selection between Xtal and LF external clock. The same glitch-free clock switching scheme as shown

in Figure 17. Synchronous Clock switching is implemented. While running on external low frequency clock, the cold start

delay does not apply and the FlagXtal is forced ‘1’. Also the OscOut input must always be driven.

Low frequency external clock selection:

•

SelExtLFck

= ‘0’ and EnXtal = ’1’.

The Xtal oscillator is selected.

•

SelExtLFck

= ’1’ and EnXtal = ’0’.

The LF external clock is selected.

•

SelExtLFck

= ’0’ and EnXtal = ’0’.

No active low frequency clock input (default state at startup)

It is not possible to have Xtal and low frequency clock active at the same time since both share the same circuit terminal

OscOut. The crystal oscillator must be disabled EnXtal=’0’ to allow for external low frequency clock input. With EnXtal=’1’

the external clock input is blocked.

The low frequency external clock on OscOut terminal may only be selected if the crystal oscillator is not active. Therfore

EnXtal

must be ‘0’, Sel32k = ‘0’, Pr1CkSel[2:0] not equal to ‘000’ , Pr2CkSel=’1’ prior to setting SelExtLFCk = ‘1’.

8.3.3

Data input on OscOut

The OscOut terminal status can be read when the Crystal Oscillator is not used (EnXtal=’0’). The reading is performed with

a read access to bit DatOscOut in register RegResStat. The OscOut input has no internal pull resistor. It may be left

floating while not used.

8.4

Clock synchronization

Besides the already described clock synchronization schemes between internal and external clocks in their respective

frequency domain, the EM6812 re-synchronizes internally the asynchronous F1 and F2 clocks (see ‘Figure 15. Clock

management block diagram’) so the CPU and the periphery always get stable clock edge conditions. The implementation is

done by synchronization of the low frequency clock (F1) with the higher speed clock (F2). For proper operation the rule F2 >

8* F1 applies.

An active peripheral clock edge issued from F1 or F2 will never occur during a CPU read or write cycle and thus allows the

CPU to manage its peripherals while they are in a quiet state. Note that this does not apply for peripherals, which run on an

asynchronous clock that has not been re-synchronized (i.e. undebounced timer clock sources). Maximum peripheral clock

selection is half the high frequency pre-divided clock.

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