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EM6812F2TP24B 数据表(PDF) 15 Page - EM Microelectronic - MARIN SA |
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EM6812F2TP24B 数据表(HTML) 15 Page - EM Microelectronic - MARIN SA |
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15 / 81 page  R EM6812 Copyright © 2005, EM Microelectronic-Marin SA 15 www.emmicroelectronic.com 5.3.4 Conflict handling The external device always has the priority against the CPU read or write operations. 2 interrupts are used to flag the occurrence of possible conflicts. Conflicts may only occur by simultaneous access to the same memory location by the external device and the CPU. Table 11. DPR interrupt flags for conflict handling CPU operation External operation Conflict description, Interrupt signification IrqDR[1] IrqDR[0] Read Write External write during CPU read. The data read by the CPU may be corrupted 0 1 Write Read External read during CPU write The CPU write operation may have failed 1 0 Write Write Concurrent writes The CPU write may have failed. 1 1 Table 12. DPR interrupt mapping Interrupt source Priority Interrupt controller connection IrqDR[1:0] 2 Int2[7:6] 5.3.5 Register overview Table 13. DPR registers RegCfgPB 0x32 Bit Name Res Reset by R/W Description 7 EnDualRAM 0 ResSys R/W Enable the Dual Port RAM 6 EnSPI 0 ResSys R/W Enable the Serial Interface function 5 EnSig1 0 ResSys R/W Connecting the internal Signal1 on PB[0] 4 EnSig2 0 ResSys R/W Connecting the internal Signal2 on PB[1] 3 EnSig3 0 ResSys R/W Connecting the internal Signal3 on PB[2] 2 EnSig4 0 ResSys R/W Connecting the internal Signal4 on PB[3] 1 - -- -- R Reads ‘0’ 0 - -- -- R Reads ‘0’ RegDPRAM0 0x0C Bit Name Res Reset by R/W Description 7-0 DPR0[7:0] 00 POR R/W Dual port RAM location 0 RegDPRAM1 0x0D Bit Name Res Reset by R/W Description 7-0 DPR1[7:0] 00 POR R/W Dual port RAM location 1 RegDPRAM2 0x0E Bit Name Res Reset by R/W Description 7-0 DPR2[7:0] 00 POR R/W Dual port RAM location 2 RegDPRAM3 0x0F Bit Name Res Reset by R/W Description 7-0 DPR3[7:0] 00 POR R/W Dual port RAM location 3 |
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