 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
EM6812F2TP24B 数据表(PDF) 9 Page - EM Microelectronic - MARIN SA |
|
|
|||||||||||||||||||||||||||||
EM6812F2TP24B 数据表(HTML) 9 Page - EM Microelectronic - MARIN SA |
|
|
9 / 81 page  R EM6812 Copyright © 2005, EM Microelectronic-Marin SA 9 www.emmicroelectronic.com 3.4 System registers Functions Register name Basic function SleepEn and Reset status RegResStat Reset Flags to identify reset source Sleep mode external Resets and RC selections RegSys1 Sleep bit and main CPU oscillator settings, reset pad configuration Xtal and CPU clock selections RegSys2 High and low frequency clock selections, Xtal enable Table 3. System registers RegResStat 0x12 Bit Name Res Reset by R/W Description 7 ResetPadFlag 0 POR RC Flag for Reset terminal, clear by write’0’ 6 ResetWDFlag 0 POR RC Flag for watchdog reset, clear by write’0’ 5 ResInpPAFlag 0 POR RC Flag for PortA input reset ,clear by write’0’ Flag is also set by BrownOut in case of DisResInp=’1’ 4 ResBwnOutFlag 0 POR RC Flag for BrownOut reset, clear by write’0’ 3 SleepEn 0 POR R/W Enables to write the Sleep bit 2 EnDebResPad 0 RegSysSlp R/W 1: Debounced reset input 0: Direct reset input 1 CkDebResPad 0 ResSys R/W 1: high speed clock (Pr1Ck[13], 8kHz) 0: low speed clock (Pr1Ck[8], 256Hz) 0 DatOscOut - - R Read data on Oscout terminal if XTAL off RegSys1 0x10 Bit Name Res Reset by R/W Description 7 Sleep 0 ResSys R/W Put the circuit in sleep mode if = ‘1’ 6 DisResetPad 0 POR R/W Disable the input pad reset if = ‘1’ 5 DisResInp 0 POR R/W Disable the port A reset input if = ‘1’ 4 FlagXtal 0 ResMain R Xtal cold start flag, Xtal ready if = ‘1’ 3 OPTCldStart[1] 0 POR R/W 2 OPTCldStart[0] 0 POR R/W Xtal cold start duration: ‘00’ = 1s, ‘10’ = 3/4s, ‘01’=1/2s, and ‘11’=1/4s. 1 FreqRange 0 ResSys R/W RC osc. frequency range selection: ‘1’=10MHz ‘0’=1MHz 0 EnRC 1 ResSys R/W Enable RC oscillator if = ‘1’ RegSys2 0x11 Bit Name Res Reset by R/W Description 7 EnXtal 0 ResMain R/W Enable Xtal oscillator if = ‘1’ 6 SelExtHFck 0 ResMain R/W Enable external clock instead of RC if = ‘1’ 5 SelHFckSource 0 ResMain R/W Select external clock PA4 if '0', PA5 if '1' 4 SelExtLFck 0 ResMain R/W Enable external clock instead of Xtal if = ‘1’ 3 -- 0 -- R/W Not used, read always ‘0’ 2 Sel32k 0 ResMain R/W CPU clock ‘1’=low freq (F1) ‘0’=high freq (F2) 1 RCDiv[1] 1 ResMain R/W 0 RCDiv[0] 1 ResMain R/W HF domain division factor for F2: ‘00’=1, ‘01’=2 , ‘10’=4, ‘11’=8 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
