EM6812F2TP24B datasheet(69/81 Pages) EMMICRO

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14.3.2 CPU Status register

The status register, used to control the interrupts and events, is an internal register to the CoolRISC CPU. It therefore does

not figure in the peripheral memory mapping. All CPU enable bits for the interrupts and the current status of the events and

the interrupts are part of this register.

Table 60. CPU status register description

Bit

Name

Reset

Reset by

R/W

Description

IE2

ResCPU

R/W

Level 2 Interrupt enable

‘1’ = enabled, ‘0’ = disabled

IE1

ResCPU

R/W

Level 1 Interrupt enable

‘1’ = enabled, ‘0’ = disabled

GIE

ResCPU

R/W*

General interrupt enable

‘1’ = enabled, ‘0’ = disabled

IN2

ResCPU

R/W

Interrupt request level 2 flag, shows CPUInt2

‘1’ = IRQ pending, ‘0’ = no IRQ

The IRQ may only take place if IN2, IE2, and GIE are set

IN1

ResCPU

R/W

Interrupt request level 1 flag, shows CPUInt1

‘1’ = IRQ pending, ‘0’ = no IRQ

The IRQ may only take place if IN1, IE1, and GIE are set

IN0

ResCPU

R/W

Interrupt request level 0 flag, shows CPUInt1

‘1’ = IRQ pending, ‘0’ = no IRQ

The IRQ may only take place if IN0 and GIE are set

EV1

ResCPU

R/W

Event request 1, input connected to VSS

EV0

ResCPU

R/W

Event request 0, input connected to DebWakeUp

*Clear General Interrupt Enable bit GIE. Special care must be taken clearing the GIE bit. If an interrupt arrives during the

clear operation the software may still branch into the interrupt routine and will set the GIE bit by the interrupt routine ending

RETI instruction. This behavior may prevent from creating 'interrupt protected' areas within your code. A suitable

workaround is to check if the GIE clearing took effect (Instruction) TSTB before executing the protected section.

14.3.3 CPU Status register pipeline exception

Another consequence of the above interrupt implementation is that several instruction sequences work in a different way

than expected. These instructions are mostly related to interrupt and event signals. For ‘normal’ instructions the pipeline is

completely transparent.

If an interrupt is set by software (i.e. write into the status register with a MOVE stat) the pipeline causes the next instruction

to be executed before the processor jumps to the interrupt subroutine. This allows one to supply a parameter to a ‘trap’ as

in Code shown below.

SETB

stat,

; trap

MOVE a

#parameter

;

If an event bit is set by software (i.e. write into the CPU status register with a MOVE stat) and if a JEV (jump on event)

instruction immediately follows the move, the jump on event will act as if the move has not been executed, since the write

into the CPU status register will occur only once the JEV has been executed. The move takes 3 cycles to be executed and

the JEV only one.

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