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EM6812F2TP24B 数据表(PDF) 12 Page - EM Microelectronic - MARIN SA |
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EM6812F2TP24B 数据表(HTML) 12 Page - EM Microelectronic - MARIN SA |
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12 / 81 page  R EM6812 Copyright © 2005, EM Microelectronic-Marin SA 12 www.emmicroelectronic.com 5 Data Memory The data memory is connected to the CoolRisc core via an 8-bit wide bi-directional data bus. It contains: • max 512Bytes of fully static RAM • Dedicated peripheral data registers for timers ports, etc. • 16 Bytes of general purpose registers. (12 Bytes LP RAM, 4 Bytes DPR) Table 5. Data memory mapping Data Memory Address ranges Description Data memory page Page 1 Indexed addressing 0x0257 (8k Instr) 0x0157 (4k or 2k Instr) 0x0060 SRAM 512 Byte (8k Instructions) 256 Byte (4 or 2k Instructions) 0x0010 All Peripherals (Timers Ports, Configurations, Interfaces, etc) 0x0000 Dual Port RAM Low Power RAM Page 0 (direct and indexed addressing) All peripherals and part of the SRAM are accessible with any addressing modes of the CoolRisc instruction set. The portion of SRAM, which is on Page 1, is addressed with any of the indexed addressing modes. 5.1 SRAM The SRAM size is adapted to the program memory size. • 512 Byte SRAM: All Versions with 8k Instruction Memory • 256 Byte SRAM: All Versions with 4k or 2k Instruction Memory. The SRAM has no reset functions, therefore is should be initialized before storing any variables. Table 6. SRAM mapping (4k or 2k Instructions Program Memory Version) Name Reset Dec Hex xx 351 0x015F : : : RAM 96 Bytes xx 256 0x0100 Indexed addressing xx 255 0x00FF : : : RAM 160 Bytes xx 96 0x0060 Direct addressing Table 7. SRAM mapping (8K Instructions Program Memory Version) Name Reset Dec Hex xx 607 0x025F : : : RAM 352 Bytes xx 256 0x0100 Indexed addressing xx 255 0x00FF : : : RAM 160 Bytes xx 96 0x0060 Direct addressing |
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