EM6812F2TP24B datasheet(10/81 Pages) EMMICRO

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EM6812

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Program Memory

All instructions to be executed are stored in the Program Memory, all general-purpose data as well as peripheral registers

values are stored in a separate data memory (see chapter 5). This special Harvard-RISC like architecture gives the core the

ability to read operands in the data memory simultaniously with one instruction fetch.

Maximum program memory size of the EM6812 is 22.5 kBytes. Each Instruction is 22 bits wide, which gives a total of 8192

Instruction words.

Program Memory is implemented as Flash memory (EM6812-Fx). I.e. EM6812-F2 which contains 2k instruction words.

The device is delivered with different program memory sizes from 8192 down to 2048 instruction words. Please refer to the

ordering information section for the different memory types and sizes.

4.1

Memory miss

The unique Memory Miss feature of the EM CoolRISC products allows operating with high-speed peripheral clocks even at

low voltage power supplys

The Memory Read Monitor (= memory miss) is an important feature ensuring correct program execution while allowing

graceful performance reduction at low voltage conditions. The access times of memory cells are dependent mainly on the

supply voltage and the temperature. Figure 4 is showing a general

case were wait states are automatically added depending on the

actual power supply voltage.

By monitoring each program memory access it can be assured that

all memory accesses are good. If necessary, wait- states will be

added.

As the supply voltage reaches V2 an interrupt

(PM_Miss_skip) is generated to signal that the Memory Read

Monitor will soon start adding wait states to ensure accurate

program execution. To be sure to always be running error free a

standard processor would have to stop its activity at this point.

Using this warning the processor can, for example, turn off not

absolutely required functions to reduce the power supply load. At

V1, the processor starts automatically adding the wait states

necessary to ensure proper operation. The processor will then

continue to operate flawlessly as the power supply voltage level

continues to descend down to the Brownout voltage, V0 in this

diagram. As the voltage falls the number of wait states will increase

as necessary to assure that the memory is read correctly at each

access.

As the Memory Read Monitor is a hardware function that uses an actual memory cell as its standard it takes into account all

of the factors that influence the real memory read time of the memory array. It works accurately for all combinations of

voltage, frequency and temperature. This guarantees stable processor operation for graceful performance reduction.

The addition of the Memory Read Monitor allows extending the working range of the application from V2 down to V0 without

compromising the operating security in any way.

Figure 5. Wait insertion versous Power supply (V2 voltage)

012

Wait states

Full speed operation

Nearing critical timing

Automatically adding

wait states to assure

error free functionality

Brownout reset

Figure 4. Read Monitor funtion

PM_Miss; Wait cycles insertion

RC 1MHz RCDiv=1

RC 10MHz RCDiv=4

RC 10MHz RCDiv=2

234

VDD

Wait Cycle insertion

No Wait Cycle

insertion

EM6812F2TP24B 数据表(PDF) 10 Page - EM Microelectronic - MARIN SA

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