EM6812F2TP24B datasheet(68/81 Pages) EMMICRO

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EM6812

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14.3

CPU Interrupt and Event handling

The CPU has three interrupt inputs of different priority. These inputs are directly connected to the peripheral interrupt

acquisition block. Each of these inputs has its own interrupt vector. Individual interrupt enabling mechanism is provided for

the 2 low priority inputs (IE1, IE2). The GIE acts as a master enable, if GIE is cleared no interrupt can reach the CPU, but

may still be stored in the interrupt acquisition block. If the hardware stack of the EM6812 is full, all interrupt inputs are

blocked. The number of implemented hardware stack levels is 4. Figure 39, CPU Interrupt architecture and Status register

shows the architectural details concerning the interrupt and event latching and its enabling mechanism.

Figure 39, CPU Interrupt architecture and Status register block

An interrupt from the peripheral acquisition block i.e. CPUInt2 is synchronized in the CPU interrupt latch and fed to the CPU

interrupt handler signal IN2 if enable bits IE2 and GIE are set and the hardware stack is not full.

Same thing applies to CPUInt1. CPUint0 is maskable only with GIE. As soon as the interrupt is latched, the GIE bit will be

automatically cleared to avoid interleaved interrupts. Reading the interrupt acquisition register will clear the pending

interrupt and at the end of the interrupt routine the RETI instruction will reinstall the GIE bit.

The CPU will loop in the interrupt routine as long as there is a CPU interrupt input active and the corresponding IE1,IE2 and

GIE are set. Refer to 14.2.2 for Interrupt acquisition Clearing.

An interrupt or Event will also clear the CPU Halt mode. The HALT mode disabling remains active as long as one of the

EV0, EV1, IN0, IN1, IN2 signals are set.

Before leaving the interrupt service routine one needs to clear the active IRQ aquisition bit (inside RegIntxx) and the

corresponding status bit (IN0, IN1, IN2) in the CoolRISC status register. Failure to do so will re-invoke the interrupt service

routine just after the preceeding RETI innstruction.

Software Interrupts and Events

The above shown CPU Interrupt handling implementation is an extension to the base structure and as such allows software

interrupts and software events to be written directly in the interrupt and event latches (write ‘1’ to CPU status register bit 0 to

4, signals status_e and status_in). Software written interrupts and events remain stored in the interrupt latch until they get

cleared again (write ‘0’ to status register bit 0 to bit 4).

The CPUEvent1 input is not used on the EM6812 and therefore reads always ‘0’ unless set by software.

The CPUEvent0 is connected to the Port A wake-up function (signal DebWakeUp), this event shows on EV0.

14.3.1 Interrupt priority

Interrupt priority is used only to select which interrupt will be processed when multiple interrupt requests occur

simultaneously. In such case the higher priority interrupt is handled first. At the end of the interrupt routine RETI the

processor will immediately go back into the interrupt routine to handle the next interrupt of highest priority.

If a high priority interrupt occurs while the CPU is treating a low priority interrupt, the pending interrupt must wait until the

GIE is enabled, usually by the RETI instruction.

HW stack not full

GIE

IE2

IE1

ck3

ck1

CPUInt0

CPUInt1

CPUInt2

CPUEvent0

(CPUEvent1=VSS)

(=DebWakeUp)

Status_e

Status_in[4:0]

interrupt and envent latch

IN2

IN1

IN0

EV0

EV1

CPU Status register

IE2

IE1

GIE

IN2

IN1

IN0

EV1

EV2

MSB

LSB

Mask

IRQ

status

Event

status

EM6812F2TP24B 数据表(PDF) 68 Page - EM Microelectronic - MARIN SA

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