EM6812F2TP24B datasheet(65/81 Pages) EMMICRO

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EM6812

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14 Interruptions

14.1

Basic features

The EM6812 handles 20 independent Interrupt sources grouped into 3 priority levels.

•

Highest Priority

: Level 0 : Prescaler clocks, PM_miss_skip

•

Medium Priority

: Level 1 : Port A input changes

•

Lowest Priority

: Level 2 : Timer compare and full, SPI , Dual port RAM

As such the EM6812 contains

•

9 external Interrupts (Port A, SPI)

•

11 internal Interrupts (Prescaler, Timer, SPI, Dual port RAM, PM_miss_skip)

Interrupt from SPI and Timer may be initialized by either external or internal actions (i.e. timer running on external clock)

Interrupts force a CALL to a fixed interrupts vector, save the program counter (PC) onto the hardware stack and reset the

general interrupt bit (GIE). If the CPU was in HALT mode prior to Interrupt then it will come back in active mode. Each

priority level has its own interrupt vector.

•

Level 1

Address 1

•

Level 2

Address 2

•

Level 0

Address 3

The GIE bit is restored when returning from interrupt with the RETI instruction. The RET instruction does not reinstall the

GIE. Nested interrupts are possible by re-enabling the GIE bit within the interrupt routine. Special care needs to be taken

when manipulating the GIE bit. See note on

Table 59. Interrupt acquisition registers.

Functions such as interrupt masking, enabling and clearing are available on different levels in the interrupt structure. At

power up or after any reset all interrupt inputs are masked and the GIE is cleared.

The Interrupt handling is split into 2 parts.

•

One part deals with the acquisition, masking and clearing of the interrupts outside of the CPU.

Interrupt acquisition, IRQ Controller

•

The 2

nd part covers all aspects of priority and interrupts enabling inside the CoolRISC core.

CPU interrupts handling

Figure 37, Interrupt top level diagram

Interrupt

controller

IRQ acquisition

IRQ sources

level 0

IRQ sources

level 1

IRQ sources

level 2

CPU

CR816L

IRQ handling

CPUInt0

CPUInt1

CPUInt2

RegInt00[7:0]

RegInt10[7:0]

RegInt20[7:0]

Reset

R/W control

IN0

IN1

IN2

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