EM6812F2TP24B datasheet(28/81 Pages) EMMICRO

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EM6812

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8.5

CPU clock selection

The CPU can run on the high frequency F2 or low frequency F1 clock domain. CPU clock selection and peripheral clock

selection are independent. If the Xtal cold-start is not finished and the LF external clock is not selected, the CPU cannot

switch on the LF clock domain, and it continuous to run on the HF clock domain until the end of the cold-start time. The bit

Sel32k

in RegSys2 controls the CPU clock selection:

•

Sel32k

= ‘0’. The CPU runs on HF clock domain.

•

Sel32k

= ‘1’. The CPU runs on LF clock domain. In this case one of the prescalers must also run with the LF clock

(either Pr1CkSel=’000’ or Pr2CkSel=’0’)

Internal or external clock sources may be chosen within both the high and low frequency clock domains. The clock

switching is based on the scheme as shown in Figure 17. Synchronous Clock switching.

8.6

Peripheral clocks generation

There are two prescalers dedicated for the peripheral clocks and the input clock can be either issued from the high or low

frequency domain. Their default setup is:

•

Prescaler2: 10-stages of RC clock division; pre-division by 8 results in a typ 62.5kHz prescaler input clock.

•

Prescaler1: 15-stage divider, ‘auto selected’ close to 32kHz input clock coming from prescaler2.

Each prescalers 8 most significant bit can be read and reset.

Figure 18. Prescaler clock selection architecture

Prescaler 1 (15 stage divider)

CkPeri_High_Freq

Pr2Ck[9:0]

Pr1Ck[15:0]

Prescaler 2 (10 stage divider)

CkPeri_Low_Freq

PrCk2[9:3]

RcDiv[2:0]

Pr2CkSel

Pr1CkSel[2:0]

DataBus

Pr1CkSource

Pr2CkSource

Clock

Selector

AutoSel

FreqRange

Int0[3:1]

(128Hz, 32Hz, 1Hz)

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