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EM6812F2TP24B 数据表(PDF) 50 Page - EM Microelectronic - MARIN SA

部件名 EM6812F2TP24B
功能描述  Ultra Low Power 8-bit FLASH Microcontroller
PDF  81 Pages
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制造商  EMMICRO [EM Microelectronic - MARIN SA]
网页  http://www.emmicroelectronic.com
标志 EMMICRO - EM Microelectronic - MARIN SA

EM6812F2TP24B 数据表(HTML) 50 Page - EM Microelectronic - MARIN SA

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R
EM6812
Copyright
© 2005, EM Microelectronic-Marin SA
50
www.emmicroelectronic.com
12.3
Registers overview:
Table 46. SPI registers
RegSPICfg
0x38
SPI configuration
Bit
Name
Res
Reset by
R/W
Description
7
Start
0
ResSysSlp
R/W
Start the transmission
6
MS2
0
ResSys
R/W
5
MS1
0
ResSys
R/W
4
MS0
0
ResSys
R/W
Selects master or slave mode. Used to select the
clock in master mode as well.
3
PosnNegShft
0
ResSys
R/W
Select the active edge of the shift register
2
MSBnLSB
0
ResSys
R/W
Select MSB or LSB first. ‘0’ = LSB first.
1
Synchro
0
ResSys
R/W
SOUT is synchronized on the opposite edge
0
Load_nShift
1
--
R
Flag indicating if the SPI is in load or transmit mode.
MS2
MS1
MS0
Mode
Clock source
0
0
0
Slave
External clock from SCLK PB[5]
0
0
1
Master
PWM1 from timer1 or timer12
0
1
0
Master
External clock from PA[5] input
0
1
1
Master
Pr2CkSource
1
0
0
Master
Pr2Ck[9]
1
0
1
Master
Pr2Ck[8]
1
1
0
Master
Pr1CkSource
1
1
1
Master
Pr1Ck[14]
RegSPIDat
0x39
SPI data register
Bit
Name
Res
Reset by
R/W
Description
7-0
SPIDat[7:0]
0
ResSys
R
Shift register status
RegSPILoad
0x3A
SPI load register
Bit
Name
Res
Reset by
R/W
Description
7-0
SPILoad[7:0]
0
ResSys
R/W
Buffer used to load the data to send through SOUT
RegCfgPB
0x32
Port B configuration
Bit
Name
Res
Reset by
R/W
Description
7
EnDualRAM
0
ResSys
R/W
Enable the Dual port RAM
6
EnSPI
0
ResSys
R/W
Enable the serial port interface
5
EnSig1
0
ResSys
R/W
Enable the internal signal 1 driving PB[0]
4
EnSig2
0
ResSys
R/W
Enable the internal signal 1 driving PB[1]
3
EnSig3
0
ResSys
R/W
Enable the internal signal 1 driving PB[2]
2
EnSig4
0
ResSys
R/W
Enable the internal signal 1 driving PB[3]
1
--
--
--
R
Read always 0
0
--
--
--
R
Read always 0
Table 47. SPI interrupt mapping
Interrupt source
Priority
IntCtrl connection
IrqSPI[1:0]
2
Int2[5:4]



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