EM6812F2TP24B datasheet(53/81 Pages) EMMICRO

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EM6812

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13.2.2 Zero-Stop mode

In “Zero-Stop” mode, the timer stops counting after reaching zero. It generates an interrupt IRQTimX and resets the Start

bit.

Startup synchronization is based on the first negative edge of the selected clock source after the start condition was fulfilled.

After the startup phase, the RegTimXLoad value is transferred into the timer and down counting starts on the next active

clock edge. Counting is based on the positive edge of the selected timer input clock source.

Figure 29. Timing diagram in Zero-Stop mode (SWStart)

Restart of the stopped timer after 0 detect

is synchronized based on the negative edge of the selected timer input clock source. The timer stop condition must be valid

for 2 full timer clock periods before being able to restart. This means that the timer can be restarted ½ clock period after the

SWStart

X bit was automatically cleared or 1½ clock timer clock cycles after the interrupt 0 detect.

Not respecting of this restart delay may prevent timer reload, its value will remain at 00 and no new IRQ will be generated

independent of the fact that its start condition may be true.

Stopping the timer during down-count

Will freeze the timer on the current value (positive timer input clock synchronization)

Restart of the stopped timer during down-count

is synchronized based on the negative edge of the selected timer input clock source. As such it acts like an initial timer start

and will start by loading the TimXLoad value and start the down-count.

Special cases apply if the timer is stopped for short periods below 1½ timer-input clocks. In such cases the count value may

be enlarged by one unit (stop seen, but restart just afterwards) or the TimXLoad may not take place (stop not seen)

For proper restart, the internal, synchronized Start signal must go low for at least 1 full clock period.

Note:

Above mentioned timer restart delay times can be drastically reduced when after going into the stop condition the timer

frequency is temporarily set to the highest available frequency (i.e. setting Pr2CkSource, NOP, going back to original clock).

Internal(ClkTim)

Internal(Stop)

Internal(Start)

synchronized

ClkIn

SwStart

TimXLoad

TimXStatus

IrqTimerX

Count down

Re-Start

(earliest possible)

CPU write

SwStart reset

by Stop

Timer Start

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