ZUSBOPTSC01ZAC datasheet(77/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

Software Interrupt Assertion

Z8FMC16100 Series Flash MCU

Product Specification

To avoid missing interrupts, ZiLOG recommends the following style of coding to clear

bits in the Interrupt Request 0 Register:

ANDX IRQ0, MASK

Software Interrupt Assertion

Program code can generate interrupts directly. Writing a 1 to the appropriate bit in the

Interrupt Request Register triggers an interrupt (assuming that interrupt is enabled). This

bit is automatically cleared when the eZ8 CPU vectors to the Interrupt Service Routine

(ISR).

The following style of coding to generate software interrupts by setting bits in the Inter-

rupt Request registers is not recommended. All incoming interrupts that are received be-

tween execution of the first LDX command and the last LDX command are lost.

The following code segment is an example of a poor coding style that can result in lost

interrupt requests:

LDX r0, IRQ0

OR r0, MASK

LDX IRQ0, r0

To avoid missing interrupts, ZiLOG recommends the following style of coding to set

bits in the Interrupt Request registers:

ORX IRQ0, MASK

Interrupt Control Register Definitions

The interrupt control registers enable individual interrupts, set interrupt priorities, and

indicate interrupt requests.

Interrupt Request 0 Register

The Interrupt Request 0 (IRQ0) Register, shown in Table 30, stores the interrupt requests

for both vectored and polled interrupts. When a request is presented to the interrupt con-

troller, the corresponding bit in the IRQ0 register becomes 1. If interrupts are globally

enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8

CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the

Interrupt Request 0 register to determine if any interrupt requests are pending.

Caution:

ZUSBOPTSC01ZAC 数据表(PDF) 77 Page - Zilog, Inc.

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